41. The offset of a particular segment varies from _________
000h to fffh
0000h to ffffh
00h to ffh
00000h to fffffh
Answer: 2. 0000h to ffffh
Explanation:
For any particular segment address, the offset address can vary within a 64 – KB range, from 0000H through FFFFH.
42. Which are the factor of cache memory?
the architecture of the microprocessor
properties of the programs being executed
size organization of the cache
all of these
Answer: 4. all of these
Explanation:
The cache performance is completely dependent on the system and software. In software, the processor checks out each loop and if a duplicate is found in the cache memory, immediately it is accessed.
The factor of cache memory is
The architecture of the microprocessor
Properties of the programs being executed
Size organization of the cache
43. ________ is usually the first level of memory access by the microprocessor.
cache memory
data memory
main memory
all of these
Answer: 1. cache memory
Explanation:
cache memory is usually the first level of memory access by the microprocessor. Cache memory also called cache, supplementary memory system that temporarily stores frequently used instructions and data for quicker processing by the central processing unit (CPU) of a computer.
44. Microprocessor references that is not available in the cache is called ________
cache hits
cache line
cache misses
cache memory
Answer: 3. cache misses
Explanation:
Microprocessor references that are not available in the cache are called cache misses.
A cache miss is an event in which a system or application makes a request to retrieve data from a cache, but that specific data is not currently in cache memory. Contrast this to a cache hit, in which the requested data is successfully retrieved from the cache.
45. Which causes the microprocessor to immediately terminate its present activity?
reset signal
interrupt signal
both
none of these
Answer: 1. reset signal
Explanation:
The reset signal causes the microprocessor to immediately terminate its present activity. Hardware is not capable of doing the initialization on its own, so a reset is used to initialize the hardware in the beginning.
46. Which is responsible for all the outside world communication by the microprocessor?
biu
piu
tiu
liu
Answer: 1. BIU
Explanation:
The Bus Interface Unit (BIU): It provides the interface of 8086 to external memory and I/O devices via the System Bus. BIU is responsible for all the outside world communication by the microprocessor.
47. INTR: it implies the__________ signal:
interrupt request
interrupt right
interrupt rongh
interrupt reset
Answer: 1. interrupt request
Explanation:
INTR implies the interrupt request signal.
INTR is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the microprocessor. The microprocessor checks the status of the INTR signal during the execution of each instruction.
48. Which of the following are the two main components of the CPU?
control unit and registers
registers and main memory
control unit and alu
alu and bus
Answer: 3. control unit and alu
Explanation:
Control unit and alu are the two main components of the CPU.
The central processing unit (CPU) consists of six main components:
control unit (CU)
arithmetic logic unit (ALU)
registers.
cache.
buses.
clock.
49. The language that the computer can understand and execute is called
machine language
application software
system program
all of the above
Answer: 1. machine language
Explanation:
The language that the computer can understand and execute is called machine language.
50. Which of the following is used as a primary storage device?
magnetic drum
prom
floppy disk
all of these
Answer: 2. prom
Explanation:
Prom is used as a primary storage device. A programmable read-only memory (PROM) is a form of digital memory where the contents can be changed once after manufacturing the device.
