Automatic Test Pattern Generation in VLSI MCQ Quiz – Objective Question with Answer for Automatic Test Pattern Generation in VLSI

21. Data retention time comes under __________ fault.

A. functional fault
B. memory fault
C. parametric fault
D. structural fault

Answer: C

One of the memory faults is a parametric fault. Some of the parametric faults are noise margin, data retention time, power consumption, output levels, etc.

 

22. In PLA, missing the cross point in OR-array leads to

A. OR fault
B. growth fault
C. missing fault
D. disappearance fault

Answer: D

In PLA, missing the cross point in AND array leads to growth fault and missing cross point in OR-array leads to disappearance fault.

 

23. In PLA, extra crosspoint in AND-array leads to

A. OR fault
B. growth fault
C. missing fault
D. disappearance fault

Answer: D

In PLA, extra crosspoint in AND-array leads to shrinkage or disappearance fault whereas extra crosspoint in OR-array leads to appearance fault.

 

24. The number of paths ___________ with number of gates.

A. increases exponentially
B. decreases exponentially
C. remains the same
D. increases rapidly

Answer: A

The number of paths increases exponentially with a number of gates. The propagation delay of the path exceeds the clock interval.

 

25. The quality of the test set is measured by

A. fault margin
B. fault detection
C. fault correction
D. fault coverage

Answer: D

The quality of a test set is measured by its fault coverage. It gives the fraction of faults that is detected by the test set.

 

26. Design for testability is considered in the production of chips because:

A. Manufactured chips are faulty and are required to be tested
B. The design of chips is required to be tested
C. Many chips are required to be tested within a short interval of time which yields timely delivery for the customers
D. All of the mentioned

Answer: C

Design for testability is considered in production for chips because many chips are required to be tested within a short interval of time which yields timely delivery for the customers.

 

27. The functions performed during chip testing are:

A. Detect faults in fabrication
B. Detect faults in design
C. Failures in functionality
D. All of the mentioned

Answer: D

The functions performed during chip testing are detecting faults in fabrication and design failures in functionality.

 

28. ATPG stands for:

A. Attenuated Transverse wave Pattern Generation
B. Automatic Test Pattern Generator
C. Aligned Test Parity Generator
D. None of the mentioned

Answer: B

ATPG is an Automatic Test Pattern Generator.

 

29. Delay fault is considered as:

A. Electrical fault
B. Logical fault
C. Physical defect
D. None of the Mentioned

Answer: B

Delay fault is considered a logical fault.

 

30. A metallic blob present between the drain and the ground of the n-MOSFET inverter acts as:

A. Physical defect
B. Logical fault as output is stuck on 0
C. Electrical fault as resistor short
D. All of the mentioned

Answer: D

A metallic blob present between the drain and the ground of the n-MOSFET inverter acts as a Physical defect, a Logical fault as output is stuck on 0, Electrical fault as resistor short.

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