21. Data retention time comes under __________ fault.
A. functional fault
B. memory fault
C. parametric fault
D. structural fault
22. In PLA, missing the cross point in OR-array leads to
A. OR fault
B. growth fault
C. missing fault
D. disappearance fault
23. In PLA, extra crosspoint in AND-array leads to
A. OR fault
B. growth fault
C. missing fault
D. disappearance fault
24. The number of paths ___________ with number of gates.
A. increases exponentially
B. decreases exponentially
C. remains the same
D. increases rapidly
25. The quality of the test set is measured by
A. fault margin
B. fault detection
C. fault correction
D. fault coverage
26. Design for testability is considered in the production of chips because:
A. Manufactured chips are faulty and are required to be tested
B. The design of chips is required to be tested
C. Many chips are required to be tested within a short interval of time which yields timely delivery for the customers
D. All of the mentioned
27. The functions performed during chip testing are:
A. Detect faults in fabrication
B. Detect faults in design
C. Failures in functionality
D. All of the mentioned
28. ATPG stands for:
A. Attenuated Transverse wave Pattern Generation
B. Automatic Test Pattern Generator
C. Aligned Test Parity Generator
D. None of the mentioned
29. Delay fault is considered as:
A. Electrical fault
B. Logical fault
C. Physical defect
D. None of the Mentioned
30. A metallic blob present between the drain and the ground of the n-MOSFET inverter acts as:
A. Physical defect
B. Logical fault as output is stuck on 0
C. Electrical fault as resistor short
D. All of the mentioned