Berkeley RISC Model MCQ Quiz – Objective Question with Answer for Berkeley RISC Model

1. How many bit register sets does RISC 1 model use?

A. 138*24
B. 138*32
C. 69*16
D. 69*32

Answer: B

RISC 1 model is developed in the 1970s and uses a large register set of 138*32 bit. These are arranged in eight overlapping windows which have 24 registers each and these windows are split so that six registers can be used during function calls.


2. Which of the following processor commercializes the Berkeley RISC model?

B. Stanford

Answer: A

The Berkeley RISC design was developed between the years 1980 and 1984 and later on, the RISC design was commercialized as a SPARC processor.


3. How many transistors does RISC 1 possess?

A. 44000
B. 45000
C. 44500
D. 45500

Answer: C

The final design of the RISC concept is called the RISC 1 which was published by ACM ISCA. It possesses 44500 transistors which can implement 31 instructions.


4. How many registers does the RISC 1 model have?

A. 68
B. 58
C. 78
D. 88

Answer: C

The RISC 1 model has 78 registers of size 32 bits.


5. Which of the architectures are made to speed up the processor?

C. program stored
D. von Neumann

Answer: B

RISC architecture is made for speeding up the processor with limited execution time whereas CISC architecture is mainly for code efficiency.


6. How did 8086 pass its control to 8087?

A. BUSY instruction
B. ESCAPE instruction
C. CONTROL instruction
D. fetch 8087

Answer: B

When 8086 comes across any floating-point arithmetic operations, it executes ESCAPE instruction code in order to pass the control of bus and instruction op-code to 8087.


7. Which of the following processor supports MMX instructions?

A. 8080
B. 80486
C. Intel Pentium
D. 80386

Answer: C

MMX instructions or multimedia extensions were introduced in Pentium processors to provide support for multimedia software running on a PC.


8. Which of the following processors has a speculative execution?

A. 80486
B. P1
C. Intel Pentium
D. Pentium pro

Answer: D

Speculative execution is executed speculatively that is, following the predicted branch paths in the code until the true path is determined. If the processor executes correctly, then the performance is gained, if not, the results are discarded and the processor continues to execute until the correct path is identified.


9. How many bit accumulators does DSP56000 have?

A. 28
B. 56
C. 112
D. 14

Answer: B

The ALU of DSP56000 has two 56-bit accumulators A and B each of which has a small register with it.


10. How many additional registers does DSP56000 have?

A. 2
B. 4
C. 6
D. 8

Answer: B

In addition to the six registers of DSP56000, it has four 24-bit registers X1, X0, Y1, Y0 which can be concatenated to form 48-bit registers X and Y.

Scroll to Top