11. The BJTs in the BICMOS circuit is in _____________ configuration.
A. Push-pull
B. Totem pole
C. Active high
D. Active low
Answer: B
In the BiCMOS circuit, the BJT transistors are in Totem pole configuration.
12. The MOSFETS are arranged in this configuration to provide __________
A. Zero static power dissipation
B. High Input impedance
C. Both zero static power dissipation and high input impedance
D. None of the mentioned
Answer: C
MOSFETs provide zero static power dissipation and high input impedance.
13. In latch-up condition, parasitic component gives rise to __________ conducting path.
A. low resistance
B. high resistance
C. low capacitance
D. high capacitance
Answer: A
In latch-up conditions, the parasitic component gives rise to low resistance conducting path between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem.
14. Latch-up can be induced by __________
A. incident radiation
B. reflected radiation
C. etching
D. diffracted radiation
Answer: A
Latch-up can be induced by glitches on the supply rail or by incident radiation.
15. How many transistors might bring up a latch-up effect in the p-well structure?
A. two
B. three
C. one
D. four
Answer: A
Two transistors and two resistances might bring up the latch-up effect in the p-well structure. These are associated with p-well and with regions of the substrate.
16. Substrate doping level should be decreased to avoid the latch-up effect.
A. true
B. false
Answer: B
An increase in substrate doping level with a consequent drop in the value of Rs can be used as a remedy for the latch-up problem.
17. What can be introduced to reduce the latch-up effect?
A. latch-up rings
B. guard rings
C. latch guard rings
D. substrate rings
Answer: B
The introduction of guard rings can reduce the effect of the latch-up problem. Guard rings are diffusions that decouple the parasitic bipolar transistors.
18. Which process produces a circuit that is less prone to the latch-up effect?
A. CMOS
B. nMOS
C. pMOS
D. BiCMOS
Answer: D
BiCMOS process produces circuits that are less likely to suffer from latch-up problems whereas CMOS circuits are very highly prone to latch-up problems.
19. Which one of the following is the main factor for reducing the latch-up effect?
A. reduced p-well resistance
B. reduced n-well resistance
C. increased n-well resistance
D. increased p-well resistance
Answer: B
One of the main factors in reducing the latch-up effect is reduced n-well resistance Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and a higher value of holding current is also required.
20. The parasitic PNP transistor has the effect of _______ carrier lifetime.
A. increasing
B. decreasing
C. exponentially decreasing
D. exponentially increasing
Answer: B
The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region.
