21. The reduction in carrier lifetime brings about __________
A. reduction in alpha
B. reduction in beta
C. reduction in current
D. reduction in voltage
Answer: B
The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.
22. To reduce the latch-up effect substrate resistance should be high.
A. true
B. false
Answer: B
To reduce the latch-up effect, substrate resistance Rs should be low. The reduction of Rs and Rw means that a larger lateral current is necessary to invite a latch-up.
23. Latch-up is the generation of __________
A. low impedance path
B. high impedance path
C. low resistance path
D. high resistance path
Answer: A
Latch-up is the generation of the low-impedance path in CMOS chips between the power supply and ground rails.
24. Latch-up is brought about by BJTs __________
A. with positive feedback
B. with negative feedback
C. with no feedback
D. without BJT
Answer: A
Latch-up occurs due to BJTs for silicon-controlled rectifiers with positive feedback and virtually short-circuit the power and ground rail.
25. Sudden transient in power can cause latch-up.
A. true
B. false
Answer: A
Sudden transient in power and ground buses are also among the reason which causes the latch-up effect.
26. BJT gain should be ______ to avoid the latch-up effect.
A. increased
B. decreased
C. should be maintained constant
D. changed randomly
Answer: B
BJT gain should be reduced by lowering the minority carrier lifetime through doping of the substrate to lower the latch-up effect.
27. The BiCMOS are preferred over CMOS due to ______________
A. Switching speed is more compared to CMOS
B. Sensitivity is less with respect to the load capacitance
C. High current drive capability
D. All of the mentioned
