Burst Interface MCQ Quiz – Objective Question with Answer for Burst Interface

1. Which of the following include special address generation and data latches?

A. burst interface
B. peripheral interface
D. input-output interfacing

Answer: A

The burst interfacing has special memory interfaces which include special address generation and data latches that help in the high performance of the processors. It takes the advantages of both the nibble mode memories and paging.


2. Which of the following makes use of the burst fill technique?

A. burst interfaces
C. peripheral interfaces
D. input-output interfaces

Answer: A

The burst interfaces use the burst fill technique in which the processor will access four words in succession, which fetches the complete cache line or written out to the memory.


3. How did burst interfaces access faster memory?

A. segmentation
C. static column memory
D. memory

Answer: C

The speed of the memory can be improved by the page mode or the static column memory which offers faster access in a single cycle.


4. Which of the following memory access can reduce the clock cycles?

A. bus interfacing
B. burst interfacing
D. dram

Answer: B

The burst interfaces reduce the clock cycles. For fetching four words with a three-clock memory, it will take 12 clock cycles but in the burst interface, it will only take five clocks to access the data.


5. How many clocks are required for the first access in the burst interface?

A. 1
B. 2
C. 3
D. 4

Answer: B

In the burst interface, the first access of the memory address requires two clock cycles and a single cycle for the remaining memory address.


6. In which of the following access, the address is supplied?

A. the first access
B. the second access
C. third access
D. fourth access

Answer: A

In the burst interface, the address is supplied only for the first access and not for the remaining accesses. External logic is required for the additional addresses for the memory interface.


7. What type of timing is required for the burst interfaces?

A. synchronous
B. equal
C. unequal
D. symmetrical

Answer: C

The burst interfacing uses unequal timing. It takes two clocks for the first access and only one for the remaining accesses which makes it unequal timing.


8. How can gate delays be reduced?
A. synchronous memory
B. asynchronous memory
C. pseudo asynchronous memory
D. symmetrical memory

Answer: A

The burst interfaced is associated with the SRAM and for the efficiency of the SRAM, it uses a synchronous memory on-chip latches to reduce the gate delays.


9. In which memory do the burst interfaces act as a part of the cache?

D. Flash memory

Answer: C

The burst interface is associated with the static RAM.


10. Which of the following uses a wrap-around burst interfacing?

A. MC68030
B. MC68040
C. HyperBus
D. US 5729504 A

Answer: B

MC68040 is developed by Motorola and uses wrap-around burst interfacing. MC68030 is also developed by Motorola but it uses a linear line fill burst. HyperBus can switch to both linear and wrap-around bursts. US 5729504 A uses a linear burst fill.

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