1. Which of the following include special address generation and data latches?
A. burst interface
B. peripheral interface
D. input-output interfacing
2. Which of the following makes use of the burst fill technique?
A. burst interfaces
C. peripheral interfaces
D. input-output interfaces
3. How did burst interfaces access faster memory?
C. static column memory
4. Which of the following memory access can reduce the clock cycles?
A. bus interfacing
B. burst interfacing
5. How many clocks are required for the first access in the burst interface?
6. In which of the following access, the address is supplied?
A. the first access
B. the second access
C. third access
D. fourth access
7. What type of timing is required for the burst interfaces?
8. How can gate delays be reduced?
A. synchronous memory
B. asynchronous memory
C. pseudo asynchronous memory
D. symmetrical memory
9. In which memory do the burst interfaces act as a part of the cache?
D. Flash memory
10. Which of the following uses a wrap-around burst interfacing?
D. US 5729504 A