21. How many types of tables are used by the processor in the protected mode?
A. 1
B. 2
C. 3
D. 4
Answer: B
There are two types of descriptor tables used by the processor in the protected mode which is GDT and LDT, that is global descriptor table and the local descriptor table respectively.
22. What does the table indicator indicate when it is set to one?
A. GDT
B. LTD
C. remains unchanged
D. toggles with GTD and LTD
Answer: B
The table indicator is a part of the selector that selects which table is to be used. If the table indicator is set to logic one, the will use the local descriptor table and if the table indicator is set to logic zero, it will use the global descriptor table.
23. What does GDTR stand for?
A. global descriptor table register
B. granularity descriptor table register
C. gate register
D. global direct table register
Answer: A
The global descriptor table register is a special register that has the linear address and the size of its own GDT. Both the global descriptor table register and local descriptor table register are located in the global descriptor table.
24. What does PMMU stands for?
A. protection mode memory management unit
B. paged memory management unit
C. physical memory management unit
D. paged multiple management units
Answer: B
The paged memory management unit is used to decrease the amount of storage needed in the page tables, that is, a multi-level tree structure is used. MC68030, PowerPC, ARM 920 uses a paged memory management unit.
25. Which of the following support virtual memory?
A. segmentation
B. descriptor
C. selector
D. paging
Answer: D
The paging mechanism supports the virtual memory. Paging helps in creating virtual address space which has a major role in memory management.
26. What does DPL in the descriptor describes?
A. descriptor page level
B. descriptor privilege level
C. direct page level
D. direct page latch
Answer: B
The descriptor privilege level is used to restrict access to the segment which helps in the protection mechanism. It acquires two bits of the descriptor.
27. What does the “S” bit describe in a descriptor?
A. descriptor type
B. small type
C. page type
D. segmented type
Answer: A
The S bit determines whether it is a system segment or a normal segment. When the S bit is set, it might be a code segment or a data segment. If the S bit clears, it is a system segment.
28. How many regions are created by the memory range in the ARM architecture?
A. 4
B. 8
C. 16
D. 32
Answer: B
The memory protection unit in the ARM architecture divides the memory into eight separate regions. Each region can be small as well as big ranging from 4 Kbytes to 4 Gbytes.
29. How many bits does the memory region in the ARM memory protection unit have?
A. 1
B. 2
C. 3
D. 4
Answer: C
The memory region possesses three bits which are the cacheable bit, bufferable bit, and access permission bit.
30. Which of the following uses a priority level for permitting data?
A. ARM memory management unit
B. ARM protection memory management unit
C. Bus interface unit
D. Execution unit
Answer: B
In the ARM protection architecture, the memory is divided into some regions of sizes 4 Kbytes to 4 Gbytes. These regions possess bits called the cacheable bit, buffer bit, and access permitted bits. The regions are numbered as per priority level for which the permission bits take precedence if any of the regions get overlapped.
