11. Which cache memory solves the cache coherency problem?
A. physical cache
B. logical cache
C. unified cache
D. Harvard cache
Answer: A
The physical cache is more efficient and can provide the cache coherency problem solved and MMU delay is kept to a minimum. PowerPC is an example of this advantage.
12. What type of cache is used in the Intel 80486DX?
A. logical
B. physical
C. Harvard
D. unified
Answer: D
The Intel 80486DX processor has a unified cache. Similarly, Motorola MPC601PC also uses the unified cache. The unified cache has the same mechanism to store both data and instructions.
13. Which of the following has a separate cache for the data and instructions?
A. unified
B. Harvard
C. logical
D. physical
Answer: B
The Harvard cache has a separate cache for the data and the instruction whereas the unified cache has the same cache for the data and instructions.
14. Which type of cache is used in the SPARC architecture?
A. unified
B. Harvard
C. logical
D. physical
Answer: C
The SPARC architecture uses a logical cache whereas most of the internal caches designed now, use a physical cache because data is not flushed out in this cache.
15. Which of the following approach uses more silicon area?
A. unified
B. Harvard
C. logical
D. physical
Answer: B
The Harvard architecture has a separate bus for data and instruction, therefore, it requires more area. It also uses more silicon area for the second set of tags and the comparators.
16. Which of the following is the biggest challenge in the cache memory design?
A. delay
B. size
C. coherency
D. memory access
Answer: C
Coherency is a major challenge in designing cache memory. The cache has to be designed by solving the problem of data coherency while remaining hardware and software compatible.
17. What arises when a copy of data is held both in the cache and in the main memory?
A. stall data
B. stale data
C. stop data
D. wait for the state
Answer: B
The stale data arises when the copy is held both in the cache memory and in the main memory. If either copy is modified, the other data become stale and the system coherency can be destroyed.
18. In which writing scheme does all the data writes go through to the main memory and update the system and cache?
A. write-through
B. write-back
C. write buffering
D. no caching of writing cycle
Answer: A
There are different writing schemes in the cache memory which increases the cache efficiency and one such is the write-through in which all the data go to the main memory and can update the system as well as the cache.
19. In which writing scheme does the cache is update but the main memory is not updated?
A. write-through
B. write-back
C. no caching of writing cycle
D. write buffering
Answer: B
The cache write-back mechanism needs a bus snooping system for the coherency. In this write-back scheme, the cache is updated first and the main memory is not updated.
20. In which writing scheme does the cache is not updated?
A. write-through
B. write-back
C. write buffering
D. no caching of writing cycle
Answer: D
The no caching write cycle does not update the cache but the data is written to the cache. If the previous data had cached, that entry is invalid and will not use. This makes the processor fetch data directly from the main memory.
