MOS Circuits Area Capacitance and Delay Unit MCQ Quiz – Objective Question with Answer for MOS Circuits Area Capacitance and Delay Unit

21. In linear mode operation, the parasitic capacitances that exists are ___________

A. Nonzero Gate to source capacitance
B. Nonzero Gate to drain capacitance
C. Zero gate to substrate capacitance
D. All of the mentioned

Answer: D

In linear-mode operation, the conducting channel exists, therefore there will be a finite amount of gate to source and gate to drain capacitances. Since the conducting channel exists, the gate to substrate capacitance is reduced to zero.

22. In saturation mode operation, gate to drain capacitance is zero due to ___________

A. Gate and drain are interconnected
B. Channel length is reduced
C. Inversion layer doesn’t exist
D. Drain is connected to ground

Answer: B

Due to the pinched off-channel, the capacitance between source to drain is reduced to zero.

23. When MOSFET is operating in the saturation region, the gate to source capacitance is?

A. 1/2*Cox*W*L
B. 2/3*Cox*W*L
C. Cox*W*L
D. 1/3*Cox*W*L

Answer: B

Due to the reduction in channel length, the gate to drain, and gate to substrate capacitance are zero, the gate to channel capacitance as seen between the gate and the source is approximately defined as 2/3*Cox*W*L.

24. The load capacitance is measured between _____

A. Output node and input node
B. Output node and Vcc
C. Output node and ground
D. Input node and ground

Answer: C

The load capacitance is measured at the output node and ground.

25. The load capacitance is equivalent to ___________

A. Sum of all lumped linear capacitances between input and output node
B. Sum of all junction capacitance between Vcc and ground
C. Sum of all junction capacitance between input and output
D. Sum of all lumped linear capacitances between output node and ground

Answer: A

The load capacitance is measured by the sum of all lumped linear capacitances between the input and output nodes.

26. Interconnect capacitance contributes to the load capacitance when the CMOS inverters are connected in a cascade configuration.

A. True
B. False

Answer: A

In cascade configuration, the load capacitance is measured by the sum of all the lumped capacitances and interconnect capacitance.

27. Interconnect capacitance is formed due to ___________

A. Junction capacitance between gate and substrate
B. Wire connecting the gates of 2 different inverters
C. Parasitic capacitance existing between metal and polysilicon connection between 2 inverters
D. All of the mentioned

Answer: C

Parasitic capacitance existing between metal and polysilicon connection between 2 inverters causes the interconnect capacitance.

28. Which of the following parameters are found using load capacitance?

A. Delay time
B. Power consumption
C. Speed of the CMOS logic
D. All of the mentioned

Answer: D

Using load capacitance, delay time, power consumption, and speed of the CMOS logic can be measured.

29. The difference output of the basic differential amplifier is taken at ___________

a) At X and ground
b) At Y and ground
c) Difference of the voltages at the gates of M1 and M2
d) Difference of the voltages between X and Y

Answer: d

The difference output of the basic differential amplifier is taken at the difference in the voltages between X and Y.

30. The Differential output of the difference amplifier is the amplification of __________
a) Difference between the voltages of input signals
b) Difference between the output of the each transistor
c) Difference between the supply and the output of the each transistor
d) All of the mentioned

Answer: a

The Differential output of the difference amplifier is the amplification of the difference between the voltages of input signals.

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