1. The conductivity of the pure silicon is raised by: A. Introducing Dopants (impurities) B. Increasing Pressure C. Decreasing Temperature D. Deformation of Lattice 2. The n-type semiconductor has _______ as the majority carriers. A. Holes B. Negative ions C. Electrons D. Positive ions 3. The majority of carriers of p-type semiconductors are: …
1. Noise in VLSI circuits means: A. Unwanted signals that arise due to vibration in the passive circuits B. Unknown signal that limits the minimum signal level that a circuit can process with acceptable quality C. Signal which undergoes distortion D. All of the mentioned 2. In probability Noise is described as: A. Random …
1. Noise Margin is: A. Amount of noise the logic circuit can withstand B. Difference between VOH and VIH C. Difference between VIL and VOL D. All of the Mentioned 2. The VIL is found from the transfer characteristics of the inverter by: A. The point where the straight line at VOH ends B. …
Noise Margin in VLSI MCQ Quiz – Objective Question with Answer for Noise Margin in VLSI Read More »
1. The electrical equivalent component for MOS structure is: A. Resistor B. Capacitor C. Inductor D. Switch 2. The Fermi potential is the function of: A. Temperature B. Doping concentration C. Difference between Fermi level and intrinsic Fermi level D. All of the mentioned 3. The direction of the electric field when the …
1. The n-MOS invertor is better than BJT in terms of: A. Fast switching time B. Low power loss C. Smaller overall layout area D. All the mentioned 2. The n-MOS inverter consists of an n-MOS transistor is driven and A. Resistor as a load B. Depletion mode n-MOS as a load C. Enhancement …
1. The conductivity of the pure silicon is raised by: A. Introducing Dopants (impurities) B. Increasing Pressure C. Decreasing Temperature D. Deformation of Lattice 2. The n-type semiconductor has _______ as the majority carriers. A. Holes B. Negative ions C. Electrons D. Positive ions 3. The majority of carriers of p-type semiconductors are: …
1. Submicron CMOS technology is A. faster B. slower C. large D. slow and large 2. In CMOS devices, which has slower performance? A. n-transistor B. p-transistor C. all of the mentioned D. none of the mentioned 3. As the channel length is scaled down, the influence of mobility A. increases B. decreases …
1. Normally-on logic uses A. depletion mode MESFET B. enhancement mode MESFET C. depletion-mode FET D. enhancement mode FET 2. Which is the approach used for normally-off logic? A. capacitor diode FET logic B. buffered FET logic C. direct-coupled FET logic D. capacitor coupled FET logic 3. __________ is needed to facilitate turn-off. …
1. MESFET circuits are formed on _____ layers. A. two B. three C. four D. five 2. If the gate-metal layer is in contact with the implant layer _____ is formed. A. diode B. transistor C. switch D. buffer 3. When an insulating layer is used in between the implant and gate metal, …
VLSI MESFET Design MCQ Quiz – Objective Question with Answer for VLSI MESFET Design Read More »
1. Inverter uses D-MESFET as A. load B. switching device C. controller D. amplifier 2. The allowable output voltage is limited by A. load resistance B. load capacitance C. barrier height D. material used for barrier 3. For the depletion-mode transistor, the gate is connected to A. Vdd B. source C. ground D. …
FET Logic Inverter MCQ Quiz – Objective Question with Answer for FET Logic Inverter Read More »
