# CMOS Logic Gate MCQ Quiz – Objective Question with Answer for CMOS Logic Gate

1. In negative logic convention, the Boolean Logic  is equivalent to:

A. +VDD
B. 0 V
C. -VDD
D. None of the mentioned

In negative logic convention, the Boolean Logic  is equivalent to 0 V and Logic ‘0’ is equivalent to +VDD.

2. In positive logic convention, the true state is represented as:

A. 1
B. 0
C. -1
D. -0

In positive logic convention, the Boolean logic ‘1’ is known to be representing the true state.

3. In a CMOS logic circuit the n-MOS transistor acts as:

B. Pull up network
C. Pull down the network
D. Not used in CMOS circuits

A static CMOS gate has an nMOS pull-down network to connect the output to 0 (GND.

4. In a CMOS logic circuit the p-MOS transistor acts as:

A. Pull down network
B. Pull up network
D. Short to ground

A static CMOS gate has a pMOS pull-up network to connect the output to VDD (1).

5. In the CMOS logic circuit, the switching operation occurs because:

1. Both n-MOSFET and p-MOSFET turn OFF simultaneously for input ‘0’ and turn ON simultaneously for input ‘1’
2. Both n-MOSFET and p-MOSFET turn ON simultaneously for input ‘0’ and turns OFF simultaneously for input ‘1’
3. N-MOSFET transistor turns ON, and the p-MOSFET transistor turns OFF for input ‘1’ and N-MOS transistor turns OFF, and the P-MOS transistor turns ON for input ‘0’
4. None of the mentioned

In the CMOS logic circuit, the switching operation occurs because the N-MOS transistor turns ON, and the P-MOS transistor turns OFF for input ‘1’ and the N-MOS transistor turns OFF, and the P-MOS transistor turns ON for input ‘0’. The networks are arranged such that one is ON and the other OFF for any input pattern.

6. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is:

A. 1 or Vdd or HIGH state
B. 0 or ground or LOW state
C. High impedance or floating(Z)
D. None of the mentioned

When both pull up and pull down transistors are OFF the high impedance for floating Z output state results.

7. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is:

A. 1 or Vdd or HIGH state
B. 0 or ground or LOW state
C. Crowbarred or Contention(X)
D. None of the mentioned

The crowbarred (or contention) X level exists when both pull-up and pull-down transistors are simultaneously turned ON. Contention between the two networks results in an indeterminate output level and dissipates static power.

8. Free running multivibrator is also called as
A. Stable multivibrator
B. Voltage control oscillator
C. Square wave oscillator
D. Pulse stretcher

Free-running multivibrator operates at a frequency that is determined by an external tuning capacitor and a resistor. On applying a dc control voltage the frequency can be shifted on either side. This frequency deviation is directly proportional to the dc control voltage and hence it is called as ‘voltage controlled oscillator’.

9. The output voltage of the phase detector is

A. Phase voltage
B. Free running voltage
C. Error voltage
D. None of the mentioned

The phase detector compares the input frequency with the feedback frequency and produces output dc voltage called as an error voltage.

10. At which state the phase-locked loop tracks any change in input frequency?

A. Free running state
B. Capture state
C. Phase-locked state
D. All of the mentioned