11. Match list I with list II which represents the three stages of a phase-locked loop (PLL).
List I
List II
1. Before input frequency applied
i. PLL-Phase locked state
2. When the input frequency applied
ii.PLL=Free running state
3. After input frequency applied
iii. PLL-Capture mode
Answer: a
Before the input is applied, the PLL is in a free-running state. Once the input frequency is applied, the VCO frequency starts to change & PLL is said to be in capture mode. When the VCO frequency continues to change until it is equal to the input frequency, the PLL is said to be in the phase-locked state.
12. What is the function of a low pass filter in a phase-locked loop?
A. Improves low-frequency noise
B. Removes high-frequency noise
C. Tracks the voltage changes
D. Changes the input frequency
Answer: B
The output voltage of a phase detector is a dc voltage and is often referred to as error voltage. This output is applied to the low pass filter which removes the high-frequency noise and produces a dc level.
13. What is the need to generate corrective control voltage?
A. To maintain the lock
B. To track the frequency change
C. To shift the VCO frequency
D. All of the mentioned
Answer: D
The output frequency(fo) of VCO is identical to input frequency(fs) except for a finite phase difference(φ), which generates a corrective control voltage to shift VCO frequency from fo to fs, thereby maintaining the lock once locked and PLL tracks the frequency changes of the input signal.
14. At what range the PLL can maintain the lock in the circuit?
A. Lock in range
B. Input range
C. Feedback loop range
D. None of the mentioned
Answer: A
The change in frequency of the incoming signal can be tracked when the PLL is locked. So, the range of frequencies over which PLL maintains the lock with the incoming signal is called the lock-in range.
15. The pull-in time depends on
A. Initial phase and frequency difference between two sign
B. Overall loop gain
C. Loop filter characteristics
D. All of the mentioned
Answer: D
The pull-in time depends on the above-mentioned characteristics to establish a lock in the PLL circuit.
16. Low L: W ratio results in ____ transistors.
A. smaller
B. bigger
C. size doesn’t depend on the ratio
D. less effective
Answer: B
The size of the transistor can be made large by a small L: W ratio and thus it has a low resistance.
17. Features which does not affect bus design are ________
A. cross-talk
B. delay factors
C. non-delay factors
D. cross-talk and delay factors
Answer: C
Cross-talk and delay factors are of significance in bus design. This occurs when many signals on the chip are propagated.
18. Which device is frequency dependent?
A. nMOS
B. CMOS
C. BiCMOS
D. pMOS
Answer: B
CMOS is frequency-dependent whereas BiCMOS is not and it exhibits a constant value for power dissipation.
19. If the current density exceeds a threshold value then metal atoms move in
A. direction of the current
B. opposite direction of the current
C. doesn’t depend on the direction of current
D. direction of the voltage
Answer: A
If the current density exceeds a threshold value then metal atoms start to move in the direction of the current.
20. At narrowing or constriction point current density is ________
A. minimum
B. maximum
C. remains low after going to high point
D. becomes high from low
Answer: B
At the narrowing or constriction point, the current density is at its highest. At these points, metal transported from the constricted regions becomes even more constricted and eventually may blow like a fuse.
