Counters Finite State Machine MCQ Quiz – Objective Question with Answer for VLSI Counters Finite State Machine

1. Counters detect only bridging faults.

A. true
B. false

Answer: B

Counters detect gate-level struck-at faults and bridging faults of the circuit under test.


2. How many test patterns are required to test the circuit using counters?

A. 2n
B. 2(n-1)
C. 2n – 1
D. 2n + 1

Answer: A

An n-bit counter generates 2 n possible test patterns which are sufficient to completely test the n-bit combinational logic circuit with no feedback.


3. The desired N value for counters is

A. less than 50
B. less than 10
C. less than 25
D. less than 70

Answer: C

The testing using the counter method is practical for the lesser values of N such as within 22 to 25 since for higher values of N more number of clock cycles are necessary.


4. The least significant bit toggles for

A. every clock cycle
B. every alternate clock cycle
C. every two clock cycles
D. every four clock cycles

Answer: A

The least significant bit toggles every clock cycle and the most significant bit toggles every halfway through and at the end of the count sequence.


5. Finite state machines are used for

A. deterministic test patterns
B. algorithmic test patterns
C. random test patterns
D. pseudo-random test patterns

Answer: B

Finite state machines are used for algorithmic test pattern generation testing for the circuit under test.


6. Address ordering minimizes the logic of finite state machines.

A. true
B. false

Answer: A

Address ordering in either ascending or descending order in the first and last loop minimizes the logic of finite state machines.


7. In finite state machine the data in and data out are

A. in the same ports
B. different ports
C. same register
D. different register

Answer: B

In finite state machines, there are separate ports for DATA IN and DATA OUT and this is a typical RAM structure.


8. _______ is used to control the read and write operations.

A. active low synchronous reset
B. active high synchronous reset
C. active low synchronous preset
D. active high synchronous preset

Answer: B

With the use of active high synchronous reset (clear) read and write operations in a finite state machine can be done.


9. Finite state machine will initially set to all zeroes.

A. true
B. false

Answer: A

The finite state machine has an initial state initialized with all 0’s whereas LFSR and CA have an initial state with any state other than all 0’s.


10. Fault coverage is ______ in finite state machines.

A. less
B. more
C. equal
D. none of the mentioned

Answer: B

The fault coverage and area overhead are better when the initial state is initialized to all 0’s in finite state machine.

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