41. A dual slope has the following specifications:
16bit counter; Clock rate =4 MHz; Input voltage=12v; Output voltage =-7v and Capacitor=0.47µF.
If the counters have cycled through 2n counts, determine the value of the resistor in the integrator.
A. 60kΩ
B. 50kΩ
C. 120kΩ
D. 100kΩ
Answer: A
Time period of the dual slope integrator,
△(t) =t2-t1 =2ncounts/clock rate
=216/4Mhz=16.38ms.
For integration,
△Vo=(-1/RC.×V×( t2-t1)
=> RC = -(12v/-7v) ×16.38ms=28.08ms
∴ R= 28.08ms =59744 ≅60kΩ.
42. A 12-bit dual ramp generation has a maximum output voltage of +12v. Compute the equivalent digital number for the analog signal of +6v.
A. 1000000000
B. 10000000000
C. 1000000000000
D. 100000000000
Answer: D
since Va =VR (N/2n)
so the digital count N= 2n×(Va/VR)
N= 212×(6/12v) = 4096×0.5 =2048.
Binary equivalent for 2048 => 100000000000.
43. Find out the resolution of 8-bit DAC/ADC?
A. 562
B. 625
C. 256
D. 265
Answer: C
The resolution is the value of LSB
Resolution =2n, where n-> number of bits
∴ Resolution =28=256 possible output values.
44. Non-linearity in the output of the converter is expressed in
A. None of the mentioned
B. Percentage of the reference voltage
C. Percentage of resolution
D. Percentage of full-scale voltage
Answer: D
Non-linearity is the measure of the deviation of actual output (ε) from the ideal straight line output (△). Therefore, it is expressed as a percentage of full-scale voltage (ε/△).
45. A binary input 000 is fed to a 3bit DAC/ADC. The resultant output is 101. Find the type of error?
A. Settling error
B. Gain error
C. Offset error
D. Linearity error
Answer: C
The offset error implies that the output of the DAC is not zero when the binary inputs are all zero.
46. How many equal intervals are present in a 14-bit D-A converter?
A. 16383
B. 4095
C. 65535
D. 1023
Answer: A
A 14-bit D-A converter has 2n-1 equal interval =214-1=16384-1=16383.
47. Resolution of a 6-bit DAC can be stated as
A. Resolution of 1 part in 63
B. 6-bit resolution
C. Resolution of 1.568% of full scale
D. All of the mentioned
Answer: D
Resolution of 6 bit DAC =VFS% /(2n-1)
=(VFS×100)/(26-1) = 1.588% of VFS and the number of interval is 26-1=63.
=> Thus, resolution of a 6 bit DAC can be stated as a resolution of 1 part in 63.
48. Find the resolution of a 10-bit AD converter for an input range of 10v?
A. 97.7mv
B. 9.77mv
C. 0.977mv
D. 977mv
Answer: B
Resolution (in volts) VFS /(2n -1)
= 10 /(210 -1)
=10/1023 =9.77mv.
49. A good converter exhibits a linearity error
A. Less than or equal to (1/2)LSB
B. Greater than equal to (1/2)LSB
C. Greater than or equal to (1/2)LSB
D. None of the mentioned
Answer: D
A good converter exhibits a linearity error of less than ±(1/2)LSB.
50. The maximum deviation between actual and ideal converter output after the removal of error is
A. Absolute accuracy
B. Relative accuracy
C. Relative /absolute accuracy
D. Linearity
Answer: B
The maximum deviation between actual and ideal converter output after the removal of error is Relative accuracy.
Relative accuracy is the maximum deviation after gain and offsets error has been removed.
51. A monotonic DAC is one whose analog output increases for
A. Decreases in digital input
B. An increases in the analog input
C. An increase in digital input
D. Decreases in the analog input
Answer: C
In a DAC, the analog input is converted into digital output. So, a monotonic DAC increases its analog output with an increase in its digital output. For example, if the output decreases when the input code change from 001 to 010, it is said to be a non-monotonic DAC.
52. All the commercially available DAC are
A. Monotonic
B. Non-monotonic
C. Either monotonic or non-monotonic
D. None of the mentioned
Answer: A
All the commercially available DACs are monotonic because the linearity error never exceeds ± (1/2) LSB at each output level.
53. The time taken for the output to settle within a specified band of its final value is referred as
A. Conversion time
B. Settling time
C. Take off time
D. All of the mentioned
Answer: B
Settling time represents the time taken for the output to settle within a specified band ± (1/2) LSB of its final value following a code change at the input (usually a full-scale change).
