Dependability Analysis for Embedded System MCQ Quiz – Objective Question with Answer for Dependability Analysis for Embedded System

21. How is the quality of the test pattern evaluated?

a) fault coverage
b) test pattern
c) size of the test pattern
d) number of errors

Answer: a

The quality of the test pattern can be evaluated based on the fault coverage. It is the percentage of potential faults that can be found for a given test pattern set, that is fault coverage equals the number of detectable faults for a given test pattern set divided by the number of faults possible due to the fault model.


22. What is DfT?

a) discrete Fourier transform
b) discrete for transaction
c) design for testability
d) design Fourier transform

Answer: c

The design of testability or DfT is the process of designing for better testability.


23. Which of the following is also known as a boundary scan?

a) test pattern
c) FSM
d) CRC

Answer: b

The JTAG is a technique for connecting scan chains of several chips and is also known as a boundary-scan.


24. What does BILBO stand for?

a) built-in logic block observer
b) bounded input bounded output
c) built-in loading block observer
d) built-in local block observer

Answer: a

The BILBO or the built-in logic block observer is proposed as a circuit combining, test response compaction, test pattern generation, and serial input/output capabilities.


25. What is CRC?

a) code reducing check
b) counter reducing check
c) counting redundancy check
d) cyclic redundancy check

Answer: d

The CRC or the cyclic redundancy check is the error detecting code that is commonly used in the storage device and the digital networks.


26. What is FSM?

a) Fourier state machine
b) finite state machine
c) fast state machine
d) free state machine

Answer: b

The FSM is a finite state machine. It will be having a finite number of states and is used to design both the sequential logic circuit and the computer programs. It can be used for testing the scan design in the testing techniques.


27. Which of the following have flip-flops that are connected to form shift registers?

a) scan design
b) test pattern
c) bit pattern
d) CRC

Answer: a

All the flip-flop storing states are connected to form a shift register in the scan design. It is a kind of test path.

Scroll to Top