DRAM Interface MCQ Quiz – Objective Question with Answer for DRAM Interface

16. Which of the following is more quickly accessed?

A. RAM
B. Cache memory
C. DRAM
D. SRAM

Answer: B

The cache memory is a small random access memory that is faster than a normal RAM. It has a direct connection with the CPU otherwise, there will be a separate bus for accessing data. The processor will check whether the copy of the required data is present in the cache memory if so it will access the data from the cache memory.

 

17. Which factor determines the effectiveness of the cache?

A. hit rate
B. refresh cycle
C. refresh rate
D. refresh time

Answer: A

The proportion of accesses of data that forms the cache hit, which measures the effectiveness of the cache memory.

 

18. Which of the following determines a high hit rate of the cache memory?

A. size of the cache
B. the number of caches
C. size of the RAM
D. cache access

Answer: A

The size of the cache increases and a large amount of data can be stored, which can access more data which in turn increases the hit rate of the cache memory.

 

19. Which of the following is a common cache?

A. DIMM
B. SIMM
C. TLB
D. Cache

Answer: C

The translation lookaside buffer is common to cache memory seen in almost all CPUs and desktops which are a part of the memory management unit. It can improve the virtual address translation speed.

 

20. Which factor determines the number of cache entries?

A. set commutativity
B. set associativity
C. size of the cache
D. number of caches

Answer: B

The set associativity is a criterion that describes the number of cache entries that could possibly contain the required data.

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