21. What is the size of the cache for an 8086 processor?
A. 64 Kb
B. 128 Kb
C. 32 Kb
D. 16 Kb
Answer: A
The 8086 processor has a 64 Kbytes cache, beyond this size, the cost will be extremely high.
22. How many possibilities of mapping does a direct-mapped cache have?
A. 1
B. 2
C. 3
D. 4
Answer: A
The direct-mapped cache only has one possibility to fetch data whereas, in a two-way system, there are two possibilities, for a three-way system, there are three possibilities, and so on. It is also known as the one-way set-associative cache.
23. Which of the following allows speculative execution?
A. 12-way set-associative cache
B. 8-way set-associative cache
C. direct-mapped cache
D. 4-way set-associative cache
Answer: C
The direct-mapped cache has the advantage of allowing a simple and fast speculative execution.
24. Which of the following refers to the number of consecutive bytes which are associated with each cache entry?
A. cache size
B. associative set
C. cache line
D. cache word
Answer: C
The cache line refers to the number of consecutive bytes which are associated with each cache entry. The data is transferred between the memory and the cache in a particular size which is called a cache line.
25. Which factor determines the cache performance?
A. software
B. peripheral
C. input
D. output
Answer: A
The cache performance is completely dependent on the system and software. In software, the processor checks out each loop and if a duplicate is found in the cache memory, immediately it is accessed.
26. What are the basic elements required for cache operation?
A. memory array, multivibrator, counter
B. memory array, comparator, counter
C. memory array, trigger circuit, a comparator
D. memory array, comparator, CPU
Answer: B
The cache memory operation is based on the address tag, that is, the processor generates the address which is provided to the cache, and this cache stores its data with an address tag. The tag is compared with the address, if they did not match, the next tag is checked. If they match, a cache hit occurs, and the data is passed to the processor. So the basic elements required are a memory array, comparator, and a counter.
27. How many divisions are possible in the cache memory based on the tag or index address?
A. 3
B. 2
C. 4
D. 5
Answer: C
There are four classifications based on the tag or index address corresponding to a virtual or physical address. They are PIPT, VIVT, PIVT, VIPT that is, physically indexed physically tagged, virtually indexed virtually tagged, physically indexed virtually tagged, virtually indexed physically tagged respectively.
28. What does DMA stand for?
A. direct memory access
B. direct main access
C. data main access
D. data memory address
Answer: A
The DMA is direct memory access that can modify the memory without the help of the processor. If any kind of memory access by DMA is to be done, it will pass a request to the processor bus and the processor provides an acknowledgment and gives them control of the bus to the DMA.
29. Which of the following cache has a separate comparator for each entry?
A. direct-mapped cache
B. fully associative cache
C. 2-way associative cache
D. 16-way associative cache
Answer: B
A fully associative cache has a comparator for each entry so that all the entries can be tested simultaneously.
30. What is the disadvantage of a fully associative cache?
A. hardware
B. software
C. memory
D. peripherals
Answer: A
The major disadvantage of the fully associative cache is the amount of hardware needed for the comparison increases in proportion to the cache size and hence, limits the fully associative cache.
