DRAM MCQ Quiz – Objective Question with Answer for DRAM

11. What does TCR stand for?

A. temperature-compensated refresh
B. temperature-compensated recovery
C. texas CAS-RAS
D. temperature CAS-RAS

Answer: A

The temperature-compensated refresh is one of the refreshing techniques used for extending the battery life by reducing the refresh rate.

 

12. How many data lines does 256*4 have?

A. 256
B. 8
C. 4
D. 32

Answer: C

There are four data lines in the memory and these different organizations of memory and these different organizations of memory are apparent when upgrading memory and it also determines how many chips are needed.

 

13. How is the number of chips required is determined?

A. number of data lines
B. the minimum number of data
C. width of the data path from the processor
D. number of data lines and the width of the data path from the processor

Answer: D

The minimum number of chips is determined by the number of data lines and the width of the data path from the processor. For example, the MC6800 family has a 16-bit wide datapath, 16*1 devices, 4*4 or 2*8 devices are needed.

 

14. Where is the memory address stored in a C program?

A. stack
B. pointer
C. register
D. accumulator

Answer: B

The memory model is defined by a range of memory address which is accessible to the program. For example, in the C program, the memory address is stored in the pointer.

 

15. Which is the term that is used to refer to the order of bytes?

A. endianness
B. memory organization
C. bit
D. register

Answer: A

Endianness defines the order of bytes, that is, whether it is big-endian or little-endian. The former represents the higher-order bits and the latter represents the lower-order bits.

 

16. Which of the following processors uses big-endian representation?

A. 8086
B. ARM
C. PowerPC
D. Zilog Z80

Answer: C

IBM’s PowerPC uses big-endian representation whereas 8086, ARM, and Zilog Z80 use little representation.

 

17. Which statement is true for a cache memory?

A. memory unit which communicates directly with the CPU
B. provides backup storage
C. a very high-speed memory to increase the speed of the processor
D. secondary storage

Answer: C

The RAM is the primary storage that directly communicates with the CPU. ROM is the secondary storage. Disk drives are capable of providing backup storage and the cache memory is a small high-speed memory that increases the speed of the processor.

 

18. Which of the following memory organization have the entire memory available to the processor at all times?

A. segmented addressing
B. paging
C. virtual address
D. linear address

Answer: D

There are two types of memory organization, linear addressing in which the entire memory is available to the processor at all times as in Motorola 6800 and the other is segmented addressing where the memory space is divided into several segments and the processor is limited to access the program instructions and data which are located in particular segments.

 

19. How many memory locations can be accessed by 8086?

A. 1 M
B. 2 M
C. 3 M
D. 4 M

Answer: A

The 8086 processor has a 20-bit address bus, hence it can access a memory of 220-1 M locations.

 

20. Which of them is a memory that is allocated to the program in the LIFO pattern?

A. stack
B. index
C. accumulator
D. base

Answer: A

A stack is a memory that is allocated to the program in the last-in, first-out pattern. The stack pointer contains the memory address of the stack.

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