DRAM Refreshing Technique MCQ Quiz – Objective Question with Answer for DRAM Refreshing Technique

The row address is placed on the address bus and the column address is held off which generates the recycle address. The address generation is done by an external hardware controller.

The Apple II personal computer has a particular memory configuration, periodically the DRAM gets blocked and is used for video memory accessing to update the screen which can refresh the DRAM.

CBR works by an internal address counter which is periodically incremented. The mechanism is based on CAS before RAS. Each time when RAS is asserted, the refresh cycle performs and the counter is incremented.

In the hidden refresh, the refresh cycle is added to the end of a normal read cycle. The RAS signal goes high and is then asserted low. At the end of the read cycle, the CAS is still asserted. This is similar to the CBR mechanism, that is, toggling of the RAS signal at the end of the read cycle starts a CBR refresh cycle.

The maximum time interval between the refresh cycles is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the manufacturer’s chip specification.

In the basic DRAM interfacing, the higher-order bits assert the RAS signal and the lower-order bits assert the CAS signal. When the access got expired, the data appears on the doubt pin and is latched by the processor.

The memory refresh is performed every 15 microseconds to remain compatible.

The direct method access limits the wait state-free operation which lowers the processor speed.

EDO RAM is a special kind of random access memory that can improve the time to read from the memory on faster microprocessors. An example of such a microprocessor is Intel Pentium.

Rambus DRAM is a synchronous memory developed by Rambus. It can replace SDRAM and is useful in high bandwidth applications.