Embedded Processor MCQ Quiz – Objective Question with Answer for Embedded Processor

102. How many bits does SPARC have?

A. 8
B. 16
C. 32
D. 64

Answer: C

It is a 32-bit RISC architecture having a 32-bit wide register bank.

Scalable Processor Architecture (SPARC) is a 32- and 64-bit microprocessor architecture developed by Sun Microsystems in 1987. SPARC is based on reduced instruction set computing (RISC).

SPARC has become a widely used architecture for hardware used with UNIX-based operating systems, including Sun’s own Solaris systems.

 

103. Which company developed SPARC?

A. intel
B. IBM
C. Motorola
D. sun microsystem

Answer: D

SPARC is developed by Sun Microsystem but different manufacturers from other companies like Intel, Texas worked on it.

Scalable Processor Architecture (SPARC) is a 32- and 64-bit microprocessor architecture developed by Sun Microsystems in 1987.

 

104. What improves the context switching and parameter passing?

A. register to window
B. large register
C. stack register
D. program counter

Answer: A

SPARC follows the Berkeley architecture model and uses register windowing in order to improve the context switching and parameter passing. It also supports superscalar operations.

 

105. How many external interrupts does the SPARC processor support?

A. 5
B. 10
C. 15
D. 20

Answer: C

SPARC processor provides 15 external interrupts which are generated by the interrupt lines IRL0-IRL3.

 

106. Which level is an in-built nonmaskable interrupt in the SPARC processor?

A. 15
B. 14
C. 13
D. 12

Answer: A

Level 15 of the SPARC processor is assigned to be a non-maskable interrupt and the remaining 14 levels are unmasked and if necessary they can be made maskable.

 

107. How many instructions does the SPARC processor have?

A. 16
B. 32
C. 64
D. 128

Answer: C

The instruction set of the SPARC processor has 64 instructions which can be accessed by load and store operation with a RISC architecture.

 

108. What is generated by an external interrupt in SPARC?

A. internal trap
B. external trap
C. memory trap
D. interfaced trap

Answer: A

In SPARC when an external interrupt is generated, an internal trap is created in the trap base register in which the current and next instructions are saved, the pipeline gets flushed and the processor turns into a supervisor mode.

 

109. When an external interrupt is generated, what type of mode does the processor support?

A. real mode
B. virtual mode
C. protected mode
D. supervisor mode

Answer: D

In SPARC when an external interrupt is called, it creates an internal trap in which the current and next instructions get saved and the mode of the processor switches to supervisor mode.

 

110. Where is the trap vector table located in the SPARC processor?

A. program counter
B. Y register
C. status register
D. trap base register

Answer: D

The trap vector table is located in the trap base register which supplies the address of the service routine. When it is completed REIT instructions are executed.

 

111. How many bits does the SPARC-V9 processor have?

A. 16
B. 32
C. 64
D. 128

Answer: C

There are three major versions of SPARC which are SPARC-V7, SPARC-V8, and SPARC-V9. The former two are 32 bits processors and the latter is a 64-bit processor.

 

112. What are the three modules in the SPARC processor?

A. IU, FPU, CU
B. SP, DI, SI
C. AX, BX, CX
D. CU, CH, CL

Answer: A

The SPARC processor has three modules which are the Integer unit, a Floating point unit, and a coprocessor unit. Each module has its own functions and an integer unit controls the overall operation of the processor.

 

113. How many floating-point registers does the FPU of the SPARC have?

A. 16 128-bit
B. 32 128-bit
C. 64 128-bit
D. 10 128-bit

Answer: A

It possesses 32 32-bit single-precision, 32 64-bit double-precision, and 16 128-bit quads precise floating registers.

 

114. Which module of SPARC contains the general-purpose registers?

A. IU
B. FPU
C. CU
D. control unit

Answer: A

The integer unit contains the general-purpose registers and it controls the overall operation and performance of the processor the memory address is also calculated by the integer unit.

 

115. What shows the brightness of the pixel in a digital signal processor?

A. luminance
B. transparent
C. chrominance
D. opaque

Answer: A

The color image of a digital signal processor has multiple channels. The brightness of the pixel is determined by luminance and the color of the pixel is determined by chrominance.

 

116. What is the color format of chrominance in a digital signal processor?

A. VGBA
B. VIBGYOR
C. White
D. RGBA

Answer: D

RGBA colors have four channels red, green, blue, and alpha, which is transparent.

 

117. Which of the following processor are designed to perform calculations in graphics rendering?

A. GPU
B. digital signal processor
C. microprocessor
D. microcontroller

Answer: A

The Graphics processing unit is designed to perform calculations in graphics rendering. Intel, NVIDIA, and AMD are dominant providers of GPU.

 

118. Which of the processor is a good match for applications such as video games?

A. GPU
B. VLIW
C. Coprocessor
D. Microcontroller

Answer: A

GPU is a graphics processing unit. Therefore, more graphical images can be created by GPU which is necessary for video games. Therefore, GPU is a good match for video games.

 

119. Which of the following statement is true for concurrency?

A. different parts of the program executes physically
B. different parts of the program execute sequentially
C. different parts of the program execute conceptually
D. different parts of the program execute sequentially and physically

Answer: C

A concurrent program executes different parts of the program conceptually, a parallel program executes different programs physically and a non-concurrent program executes the program in sequential order.

 

120. Which is an imperative language?

A. C program
B. SQL
C. XQuery
D. Concurrent model of HDL

Answer: A

Imperative language is one that executes the program in sequential order. C program is an example of imperative language, SQL and XQuery are examples of declarative languages or non-imperative language. The concurrent model in HDL is a hardware description language that executes the program concurrently.

 

121. Which of the following instructions supports parallel execution?

A. VLIW
B. TTA
C. ALU operation
D. Test-and-set instructions

Answer: A

VLIW is a very long instruction word that receives many instructions and is executed in one instructed word.

VLIW is majorly designed for instruction-level parallel (ILP) that is, it can execute codes concurrently or parallel for some time.

TTA is a transport-triggered architecture which is a type of CPU design that programs controlling the internal buses of the processor.

Test-and-set is used to write to a memory location and return its old values. ALU is used to perform arithmetic and logic operations.

 

122. Who invented VLIW architecture?

A. Josh Fisher
B. John Ellis
C. John Ruttenberg
D. John O’Donnell

Answer: A

Josh Fisher from Yale Universities invented the concept of VLIW architecture. John Ellis described the VLIW compiler. John Ruttenberg develops some important algorithms in scheduling.

 

123. What is ILP?

A. instruction-level parallelism
B. instruction-level panel
C. instruction-language panel
D. inter-language parallelism

Answer: A

ILP is instruction-level parallelism. It is a processor which supports instruction-level parallelism and can perform multiple independent operations in every instruction cycle.

Basically, there are four types of instructions. These are CISC instructions, subword parallelism, superscalar, and VLIW.

 

124. Which ILP supports the ALU division?

A. Subword parallelism
B. CISC
C. Superscalar
D. VLIW

Answer: A

Subword parallelism supports the ALU division. In subword parallelism, the wide ALU is divided into smaller slices which enable simultaneous arithmetic and logical operations.

 

125. Which is a vector processor?

A. Subword parallelism
B. CISC
C. Superscalar
D. VLIW

Answer: A

Subword parallelism is a form of vector processing. A vector processor is one whose instruction set includes operations on multiple data elements simultaneously.

 

126. Which of the following architecture supports out-of-order execution?

A. RISC
B. CISC
C. Superscalar
D. Subword parallelism

Answer: C

The superscalar architecture supports out-of-order execution in which the instructions later in the stream are executed before earlier instructions.

 

127. Which is an example of superscalar architecture?

A. Pentium 4
B. 8086
C. 80386
D. Pentium pro

Answer: A

Pentium 4 is a single-core CPU used in desktops and laptops that are proposed by Intel. It has Netburst architecture.

 

128. Which of the following is a combination of several processors on a single chip?

A. Multicore architecture
B. RISC architecture
C. CISC architecture
D. Subword parallelism

Answer: A

The Multicore machine is a combination of many processors on a single chip. The heterogeneous multicore machine also combines a variety of processor types on a single chip.

 

129. Which is an example of a multi-core processor which possesses 10 cores?

A. Intel Xeon E7-2850
B. AMD Phenom IIX2
C. Intel core duo
D. AMD Phenom IIX3

Answer: A

Intel Xeon E7-2850 has ten cores whereas AMD Phenom IIx2 and Intel core duo have two cores and AMD Phenom IIX3 has three cores.

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