Embedded System Memory Management MCQ Quiz – Objective Question with Answer for Embedded System Memory Management

DIMM is a special version of SIMM which is a 168-bits wider bus and looks similar to a larger SIMM. The wider bus increases the memory speed and change in supply voltage.

The SIMM is basically a subassembly, not a package. It is a small board that possesses a finger connection on the bottom and sufficient memory on the board in order to make up the required configuration.

For increasing the speed and reducing the power consumption, it is necessary to reduce the power supply. Today’s CPUs and memories have a 3.3V supply or even lower instead of the signal level from 0 to 5V. DIMMs are described by their voltage, speed, and memory type respectively as 3.3V 133MHz SDRAM DIMM.

The Single-in-line package is the same as that of SIMM, in which the finger connections are replaced by a single row of pins. SIP took the popularity of SIMM but nowadays it is rarely seen.

The access time of the memory is defined as the maximum time taken by the chip to read/write data and it is very important to match the access time to the design. For example, MCM51000AP10 has a 100ns access time for the memory.

The DRAM needs to be periodically refreshed and the very basic technique is a special refresh cycle, during these cycles no other access is permitted. The whole chip is refreshed within a particular time period otherwise, the data will be lost.

The time required for refreshing the whole chip is known as refresh time. The number of access needed to complete refresh is called the number of cycles. The number of cycles divided by the refresh time gives the refresh rate.

There are two refresh rates used in common. They are a standard refresh rate of 15.6 microseconds and 125 microseconds which is the extended form.

Each of the refresh cycles is approximate twice the length of the normal access, for example, a 70ns DRAM has a refresh cycle time of 130ns.

When the refresh cycle in a DRAM is running, it will not access data, so the processor will have to wait for its data. This arises some timing issues.