Embedded System Memory Management MCQ Quiz – Objective Question with Answer for Embedded System Memory Management

A 4M by 1 DRAM has 1024 refresh cycles. The bursting delay will be 0.2ms that are, the worst-case delay is 1024 times larger than that of the single refresh cycle. The distributed delay is about 170ns.

Most of the system uses the distributed method and depending on the size of the time-critical code, the number of refresh cycles can be calculated.

The software refresh acts by using a routine to periodically cycle through the memory and refresh. It uses a timer in the program to generate an interrupt. This interrupt performs the refreshing part in the DRAM.

Debugging in software refresh is very difficult to perform because they may stop the refreshing and if the refreshing is stopped, the contents get lost.

CBR that is, CAS before RAS refresh is the one that is commonly used. It has low power consumption quality because it does not have an address bus and the buffers can be switched off. It is worked by using an internal address counter which is stored on the memory chip itself and this can be incremented periodically.

The row address is placed on the address bus and the column address is held off which generates the recycle address. The address generation is done by an external hardware controller.

The Apple II personal computer has a particular memory configuration, periodically the DRAM gets blocked and is used for video memory accessing to update the screen which can refresh the DRAM.

CBR works by an internal address counter which is periodically incremented. The mechanism is based on CAS before RAS. Each time when RAS is asserted, the refresh cycle performs and the counter is incremented.

In the hidden refresh, the refresh cycle is added to the end of a normal read cycle. The RAS signal goes high and is then asserted low. At the end of the read cycle, the CAS is still asserted. This is similar to the CBR mechanism, that is, toggling of the RAS signal at the end of the read cycle starts a CBR refresh cycle.

The maximum time interval between the refresh cycles is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the manufacturer’s chip specification.