106. Which of the following generic DMA controllers contains a base address register and an auto-incrementing counter?
A. address bus
B. data bus
C. bus requester
D. address generator
Answer: D
The generic controller has several components associated with it for controlling the operation and one such is the address generator. It consists of the base address register and an auto-incrementing counter which increment the address after every transfer.
107. Which of the following is used to transfer the data from the DMA controller to the destination?
A. data bus
B. address bus
C. request bus
D. interrupt signal
Answer: A
The data bus is used for the transmission of data from the DMA controller to the destiny. The DMA controller can directly select the peripheral in some cases in which the data transfer is made from the peripheral to the memory.
108. Which of the following is used to request the bus from the main CPU?
A. data bus
B. address bus
C. bus requester
D. interrupt signal
Answer: C
The bus requester requests the bus from the main CPU. In earlier design, the processor bus does not support the multi-master system and there were no bus request signals. In such cases, the processor clock was extended.
109. Which signal can identify the error?
A. data bus
B. address bus
C. bus requester
D. interrupt signal
Answer: D
The interrupt signal can identify the error that occurred in the DMA controller. This makes the processor reprogram the DMA controller for a different transfer.
110. Which signal allows the DMA controller to select the peripheral?
A. local peripheral control
B. global peripheral control
C. address bus
D. data bus
Answer: A
The local peripheral control allows the DMA controller to select the peripheral.
111. Which of the following is also known as implicit address?
A. dual address model
B. single address model
C. 1D model
D. 2D model
Answer: B
The single address model is also known as the implicit model because the second address is implied and is not directly given, that is, the source address is not supplied.
112. Which address mode uses two addresses and two accesses to transfer the data between the peripheral and the memory?
A. dual address model
B. 1D model
C. 2D model
D. 3D model
Answer: A
The dual address mode supports two addresses and two accesses for transferring data between a peripheral or memory and another memory location.
113. Which of the following address mode uses a buffer to hold data temporarily?
A. 1D model
B. 2D model
C. dual address model
D. 3D model
Answer: C
The dual address mode supports two addresses and two accesses for transferring data between a peripheral or memory and another memory location, which also consumes two bus cycles and a buffer within the DMA controller to hold data temporarily.
114. Which of the following model can implement a circular buffer?
A. dual address mode
B. 1D model
C. 2D model
D. 3D model
Answer: B
The 1D model can implement a circular buffer which makes an automatic reset to bring the address back to the beginning.
115. Which of the following uses an address and a counter to define the sequence of addresses?
A. dual address mode
B. 2D model
C. 1D model
D. 3D model
Answer: C
The 1D model of the DMA controller uses an address location and a counter to define the address sequence which is used during the DMA cycles.
116. Which of the following is used to calculate an offset to the base address?
A. single address mode
B. dual address mode
C. 1D model
D. 2D model
Answer: D
An address stride is specified which can be used for calculating the offset to the base address at the terminal of the count. This address stride is used in the 2D model of the DMA controller.
117. Which can provide an address stride?
A. single address mode
B. dual address mode
C. 1D model
D. 2D model
Answer: D
In the 2D model of the DMA controller, an address stride is specified which can be used for calculating the offset to the base address at the terminal of the count.
118. How is the count register can be splitted?
A. 2
B. 3
C. 4
D. 5
Answer: A
In the 2D model of the DMA controller, in addition to the address stride there is a count register that can be split into two, in which one register is used to specify the count for the block, and the second register is used to define the total number of blocks or the bytes to be transferred.
119. Which of the following has the ability to change the stride automatically?
A. 1D model
B. 2D model
C. 3D model
D. dual address mode
Answer: C
In the 3D model of the DMA controller, it has the ability to change the address stride automatically so that blocks of different sizes and strides can be created.
120. Which is used to prioritize multiple requests?
A. dual address mode
B. single address mode
C. arbitration
D. chaining
Answer: C
The arbitration is used to provide priority for multiple access. This uses a priority scheme that may offer fair priority to the one channel, or a high priority to the other channel, and so on. Such a condition is otherwise known as a round-robin condition in which the priority is equally divided.
