Embedded System Structure MCQ Quiz – Objective Question with Answer for Embedded System Structure

81. What is EDO RAM?

A. extreme data operation
B. extended direct operation
C. extended data out
D. extended DRAM out

Answer: C

EDO RAM is a special kind of random access memory that can improve the time to read from the memory on faster microprocessors. An example of such a microprocessor is Intel Pentium.

 

82. What is RDRAM?

A. refresh DRAM
B. recycle DRAM
C. Rambus DRAM
D. refreshing DRAM

Answer: C

Rambus DRAM is a synchronous memory developed by Rambus. It can replace SDRAM and is useful in high bandwidth applications.

 

83. Which of the following can transfer up to 1.6 billion bytes per second?

A. DRAM
B. RDRAM
C. EDO RAM
D. SDRAM

Answer: B

The Rambus RAM can transfer up to 1.6 billion bytes per second. It possesses a RAM controller, a bus that connects the microprocessor and the device, and random access memory.

 

84. Which of the following cycle is larger than the access time?

A. write cycle
B. set up a time
C. read cycle
D. hold time

Answer: C

The read cycle in the DRAM interfacing is larger than the access time because of the precharge time.

 

85. Which mode of operation selects an internal page of memory in the DRAM interfacing?

A. page interleaving
B. page mode
C. burst mode
D. EDO RAM

Answer: B

In the page mode operation, the row address is provided as normal but the RAS signal is left asserted. This, in turn, selects an internal page within the DRAM memory where any bit of data can be accessed by placing the column address and asserting CAS.

 

86. What is the maximum time that the RAS signal can be asserted in the page mode operation?

A. 5 microseconds
B. 10 microseconds
C. 15 microseconds
D. 20 microseconds

Answer: B

The maximum time that the RAS signal can be asserted during the page mode operation is about 10 microseconds. But this is a major disadvantage for page mode operation, that is, the standard PCs have a maximum time of 15 microseconds for the refresh cycle.

 

87. Which of the following mode of operation in the DRAM interfacing has a page boundary?

A. burst mode
B. EDO RAM
C. page mode
D. page interleaving

Answer: C

The page mode operation has memory cycles that exhibit some form of locality, that is, stay within the page boundary which causes the page missing when there is access outside the page boundary and two or more wait states.

 

88. Which mode offers the banking of memory in the DRAM interfacing technique?

A. page mode
B. basic DRAM interfacing
C. page interleaving
D. burst mode

Answer: C

The accessing of data outside the page boundary can cause the missing pages in the page mode operation. So a program has to operate for frequently accessing data thereby, increasing the efficiency in the page selection. One such model is the page interleaving mode in which the memory is divided into different banks, depending on the number of memories installed.

 

89. Which of the following has a fast page mode RAM?

A. burst mode
B. page interleaving
C. EDO memory
D. page mode

Answer: C

Extended data out memory is a fast page mode RAM that has a faster cycling process which makes EDO memory a faster page mode access.

 

90. Which mode reduces the need for fast static RAMs?

A. page mode
B. page interleaving
C. burst mode
D. EDO memory

Answer: C

The page mode and nibble mode devices can provide data fastly when the new column address is given. In burst mode operation, the processor can fetch more data than it needs and keeps the remaining data in an internal cache for future use which can reduce the need for fast static RAMs.

 

91. Which of the following is also known as hyper page mode enabled DRAM?

A. page mode
B. EDO DRAM
C. burst EDO DRAM
D. page interleaving

Answer: B

The EDO DRAM is also known as hyper page mode enables DRAM because of the faster page mode operation along with some additional features.

 

92. What does BEDO DRAM stand for?

A. burst EDO DRAM
B. buffer EDO DRAM
C. BIBO EDO DRAM
D. bilateral EDO DRAM

Answer: A

The burst EDO DRAM is evolved from the EDO DRAM and it can access four memory addresses in one burst. It also supports pipeline stages which allow the page access cycle into two parts.

 

93. Which of the following is more quickly accessed?

A. RAM
B. Cache memory
C. DRAM
D. SRAM

Answer: B

The cache memory is a small random access memory that is faster than a normal RAM. It has a direct connection with the CPU otherwise, there will be a separate bus for accessing data. The processor will check whether the copy of the required data is present in the cache memory if so it will access the data from the cache memory.

 

94. Which factor determines the effectiveness of the cache?

A. hit rate
B. refresh cycle
C. refresh rate
D. refresh time

Answer: A

The proportion of accesses of data that forms the cache hit, which measures the effectiveness of the cache memory.

 

95. Which of the following determines a high hit rate of the cache memory?

A. size of the cache
B. the number of caches
C. size of the RAM
D. cache access

Answer: A

The size of the cache increases and a large amount of data can be stored, which can access more data which in turn increases the hit rate of the cache memory.

 

96. Which of the following is a common cache?

A. DIMM
B. SIMM
C. TLB
D. Cache

Answer: C

The translation lookaside buffer is common to cache memory seen in almost all CPUs and desktops which are a part of the memory management unit. It can improve the virtual address translation speed.

 

97. Which factor determines the number of cache entries?

A. set commutativity
B. set associativity
C. size of the cache
D. number of caches

Answer: B

The set associativity is a criterion that describes the number of cache entries that could possibly contain the required data.

 

98. What is the size of the cache for an 8086 processor?

A. 64 Kb
B. 128 Kb
C. 32 Kb
D. 16 Kb

Answer: A

The 8086 processor has a 64 Kbytes cache, beyond this size, the cost will be extremely high.

 

99. How many possibilities of mapping does a direct-mapped cache have?

A. 1
B. 2
C. 3
D. 4

Answer: A

The direct-mapped cache only has one possibility to fetch data whereas, in a two-way system, there are two possibilities, for a three-way system, there are three possibilities, and so on. It is also known as the one-way set-associative cache.

 

100. Which of the following allows speculative execution?

A. 12-way set-associative cache
B. 8-way set-associative cache
C. direct-mapped cache
D. 4-way set-associative cache

Answer: C

The direct-mapped cache has the advantage of allowing a simple and fast speculative execution.

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