142. What type of timing is required for the burst interfaces?
A. synchronous
B. equal
C. unequal
D. symmetrical
Answer: C
The burst interfacing uses unequal timing. It takes two clocks for the first access and only one for the remaining accesses which makes it unequal timing.
143. How can gate delays be reduced?
A. synchronous memory
B. asynchronous memory
C. pseudo asynchronous memory
D. symmetrical memory
Answer: A
The burst interfaced is associated with the SRAM and for the efficiency of the SRAM, it uses a synchronous memory on-chip latches to reduce the gate delays.
144. In which memory do the burst interfaces act as a part of the cache?
A. DRAM
B. ROM
C. SRAM
D. Flash memory
Answer: C
The burst interface is associated with the static RAM.
145. Which of the following uses a wrap-around burst interfacing?
A. MC68030
B. MC68040
C. HyperBus
D. US 5729504 A
Answer: B
MC68040 is developed by Motorola and uses wrap-around burst interfacing. MC68030 is also developed by Motorola but it uses a linear line fill burst. HyperBus can switch to both linear and wrap-around bursts. US 5729504 A uses a linear burst fill.
146. Which of the following is a Motorola protocol product?
A. MCM62940
B. Avalon
C. Slave interfaces
D. AXI slave interfaces
Answer: A
MCM62940 protocol is developed by Motorola, whereas Slave interfaces, and AXI slave interfaces are for ARM. Avalon is developed by Altera.
147. Which of the following uses a linear line fill interfacing?
A. MC68040
B. MC68030
C. US 74707 B2
D. Hyper Bus
Answer: B
MC68030 uses a linear burst fill whereas MC68040, US 74707 B2 uses wrap-around burst interfacing. HyperBus can switch to both linear and wrap-around interfacing.
148. Which of the following protocol matches the Intel 80486?
A. MCM62940
B. MCM62486
C. US 74707 B2
D. Hyper Bus
Answer: B
The MCM62486 has an on-chip counter that matches the Intel 80486 and is developed by Motorola.
149. Which of the following protocol matches the MC68040?
A. MCM62486
B. US 5729504 A
C. HyperBus
D. MCM62940
Answer: D
The MCM62940 and MCM62486 are the specific protocols developed by Motorola, in which the MCM62940 has an on-chip counter which matches the wrap-around burst interfacing of the MC68040.
150. The modified bit is also known as
A. dead bit
B. neat bit
C. dirty bit
D. invalid bit
Answer:c
The dirty bit is said to be set if the processor modifies its memory. This bit indicates that the associative set of blocks regarding the memory is modified and has not yet been saved to the storage.
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151. Which of the following have an 8 KB page?
A. DEC Alpha
B. ARM
C. VAX
D. PowerPC
Answer: A
DEC Alpha divides its memory into 8KB pages whereas VAX is a small page that is only 512 bytes in size. PowerPC pages are normally 4 KB and ARM is having 4 KB and 64 KB pages.
152. Which of the following address is seen by the memory unit?
A. logical address
B. physical address
C. virtual address
D. memory address
Answer: B
The logical address is the address generated by the CPU. It is also known as a virtual address. The physical address is the address that is seen by the memory unit.
153. Which of the following modes offers segmentation in the memory?
A. virtual mode
B. real mode
C. protected mode
D. memory mode
Answer: C
The main memory can be split into small blocks by the method of paging and segmentation and these mechanisms are possible only in protected mode.
154. Which of the following is necessary for the address translation in the protected mode?
A. descriptor
B. paging
C. segmentation
D. memory
Answer: A
The address translation from the logical address to the physical address partitions the main memory into different blocks which is called segmentation. Each of these blocks has a descriptor that possesses a descriptor table. So the size of every block is very important for the descriptor.
155. What does “G” in the descriptor entry describe?
A. gain
B. granularity
C. gate voltage
D. global descriptor
Answer: B
The granularity bit controls the resolution of the segmented memory. When it is set to logic one, the resolution is 4 KB. When the granularity bit is set to logic zero, the resolution is 1 byte.
156. How many types of tables are used by the processor in the protected mode?
A. 1
B. 2
C. 3
D. 4
Answer: B
There are two types of descriptor tables used by the processor in the protected mode which is GDT and LDT, that is global descriptor table and the local descriptor table respectively.
157. What does the table indicator indicate when it is set to one?
A. GDT
B. LTD
C. remains unchanged
D. toggles with GTD and LTD
Answer: B
The table indicator is a part of the selector that selects which table is to be used. If the table indicator is set to logic one, the will use the local descriptor table and if the table indicator is set to logic zero, it will use the global descriptor table.
158. What does GDTR stand for?
A. global descriptor table register
B. granularity descriptor table register
C. gate register
D. global direct table register
Answer: A
The global descriptor table register is a special register that has the linear address and the size of its own GDT. Both the global descriptor table register and local descriptor table register are located in the global descriptor table.
159. What does PMMU stands for?
A. protection mode memory management unit
B. paged memory management unit
C. physical memory management unit
D. paged multiple management units
Answer: B
The paged memory management unit is used to decrease the amount of storage needed in the page tables, that is, a multi-level tree structure is used. MC68030, PowerPC, ARM 920 uses a paged memory management unit.
160. Which of the following support virtual memory?
A. segmentation
B. descriptor
C. selector
D. paging
Answer: D
The paging mechanism supports the virtual memory. Paging helps in creating virtual address space which has a major role in memory management.
