Embedded systems memory management MCQ Quiz – Objective Question with Answer for Embedded systems memory management

Coherency is a major challenge in designing cache memory. The cache has to be designed by solving the problem of data coherency while remaining hardware and software compatible.

The stale data arises when the copy is held both in the cache memory and in the main memory. If either copy is modified, the other data become stale and the system coherency can be destroyed.

There are different writing schemes in the cache memory which increases the cache efficiency and one such is the write-through in which all the data go to the main memory and can update the system as well as the cache.

The cache write-back mechanism needs a bus snooping system for the coherency. In this write-back scheme, the cache is updated first and the main memory is not updated.

The no caching write cycle does not update the cache but the data is written to the cache. If the previous data had cached, that entry is invalid and will not use. This makes the processor fetch data directly from the main memory.

The no caching of the write cycle seems to be wasteful because it does not update the cache, and if any previous data is cached, that entry might be an error and is not used. So the processor access data from the main memory but this writing scheme forms the backbone of the bus snooping system for the coherency issue.

There is four main writing scheme in the cache memory which is, write-through, write-back, no caching of the write cycle, and write buffer. All these writing schemes are designed for bus snooping which can reduce the coherency.

The write buffer is slightly similar to the write-through mechanism in which data is written to the main memory but in the write buffer mechanism, data writes to the main memory via a buffer.

A write-allocate cache allocates the entries in the cache for any data that is written out. If the data is transferred to the external memory so that, when it is accessed again, the data is already waiting in the cache. It works efficiently if the size of the cache is large and it does not overwrite even though it is advantageous.

The bus snooping mechanism uses a combination of cache tag status, write policies, and bus monitoring to ensure coherency. MC88100 or MC88200 uses a bus snooping mechanism.

The problem of cache coherency lead to the formation of two standard mechanisms called MESI and MEI protocol. MC88100 has a MESI protocol and MC68040 uses an MEI protocol.

The MESI protocol is also known as the Illinois protocol because of its formation at the University of Illinois.

The MESI protocol supports a shared state which is a formal mechanism for controlling the cache coherency by using the bus snooping techniques. MESI refers to the states that cached data can access. In the MESI protocol, multiple processors can cache shared data.

MEI protocol is less complex and easy to implement. It does not allow a shared state for the cache.

MPC601 uses a MESI protocol, that is they have a shared state for data accessing in the cache. It can reduce the cache coherency but the cache coherency is processor-specific. So different processors have different cache coherency implementations.

The burst interfacing has special memory interfaces which include special address generation and data latches that help in the high performance of the processors. It takes the advantages of both the nibble mode memories and paging.

The burst interfaces use the burst fill technique in which the processor will access four words in succession, which fetches the complete cache line or written out to the memory.

The speed of the memory can be improved by the page mode or the static column memory which offers faster access in a single cycle.

The burst interfaces reduce the clock cycles. For fetching four words with a three-clock memory, it will take 12 clock cycles but in the burst interface, it will only take five clocks to access the data.

In the burst interface, the first access of the memory address requires two clock cycles and a single cycle for the remaining memory address.

In the burst interface, the address is supplied only for the first access and not for the remaining accesses. External logic is required for the additional addresses for the memory interface.