A. load
B. switching device
C. controller
D. amplifier
Answer: A
Direct-coupled FET logic inverter uses both depletion and enhancement type devices. E-MESFET is used as a switching device and D-MESFET is used as a load.
2. The allowable output voltage is limited by
A. load resistance
B. load capacitance
C. barrier height
D. material used for barrier
Answer: C
The design of the inverter is similar to silicon nMOS circuitry and the allowable output voltage is limited by the barrier height of the Schottky gate diode.
3. For the depletion-mode transistor, the gate is connected to
A. Vdd
B. source
C. ground
D. drain
Answer: B
For the depletion-mode transistor, the gate is connected to the source and it is always on and only the characteristic curve Vgs=0 is suitable.
4. In DCFL inverter, enhancement mode device is called as
A. pull-down transistor
B. pull up transistor
C. buffer
D. combiner
Answer: A
In a direct-coupled FET logic inverter, the depletion mode device is called the pull-up, and the enhancement mode device is called as pull-down transistor.
5. Maximum voltage across enhancement mode device corresponds to the minimum voltage across depletion mode device.
A. true
B. false
Answer: A
In a direct-coupled FET logic inverter, maximum voltage across the enhancement mode device corresponds to the minimum voltage across the depletion-mode transistor.
6. When current begins to flow, output voltage
A. increases
B. decreases
C. remains constant
D. does not get affected
Answer: B
When Vin exceeds the threshold voltage, the current begins to flow. Then the output voltage Vout decreases and the transistor becomes resistive.
7. Inverter threshold voltage is the point where
A. Vin = Vt
B. Vout = Vt
C. Vin = Vout
D. Vout is lesser than Vin
Answer: C
The point at which Vout = Vin, is denoted as Vinv. The transfer characteristic and Vinv can be shifted by variation of the ratio of pull-up to pull-down resistances.
8. For equal margin, Vinv is set as ______ of logic voltage swing.
A. equal
B. half of
C. one third
D. twice
Answer: B
Since the logic high level is limited by barrier potential then for equal margins Vinv is set to half of the logic voltage swing.
9. For E-MESFET, Vinv is set in midway between
A. Vdd and Vss
B. Vt and Vin
C. Vt and Vout
D. barrier potential and ground
Answer: D
In a pull-down device that is E-MESFET, the inverter threshold voltage Vinv is set midway between barrier potential and ground.
10. To improve packing density, gate length should be smaller.
A. true
B. false
Answer: B
To improve packing density, the gate length should be larger for the pull-up device. This will reduce drain to source saturation current.
