NOR flash memory is a storage device. It has a slow write speed compared to NAND-type flash. Typical NOR-type flash does not need error-correcting codes.
12. Which allows random access to read?
A. NOR-type flash
B. NAND type flash
C. all of the mentioned
D. none of the mentioned
Answer: A
The interface provided for reading and writing is different. NOR-type flash provides random access for reading whereas NAND-type flash provides page access.
13. Which has high storage capacity?
A. NOR-type flash
B. NAND type flash
C. all of the mentioned
D. none of the mentioned
Answer: B
NAND-type flash memory has different connections and interfaces when compared to NOR-type flash. Storage capacity is more in NAND-type flash than NOR-type flash memory.
14. Realization of JK flipflop is based on
A. n-pass transistor
B. p-pass transistor
C. CMOS
D. BiCMOS
Answer: A
The realization of the JK flip flop is based on the n-pass transistor and on inverters only.
15. Static RAM uses ____________ transistors.
A. four
B. five
C. six
D. seven
Answer: C
Static RAM uses six transistors. In this RAM cell, read and write operations use the same port.
16. Which method is used to determine structural defects?
A. deterministic test pattern
B. algorithmic test pattern
C. random test pattern
D. exhaustive test pattern
Answer: A
Deterministic test patterns are used to detect specific faults or structural faults for a circuit under test.
17. Which is known as the stored test pattern method?
A. deterministic test pattern
B. algorithmic test pattern
C. random test pattern
D. exhaustive test pattern
Answer: A
The deterministic test pattern method is also known as the stored test pattern method in the context of BIST applications.
18. Which method uses a finite state machine for developing the test pattern?
A. deterministic test pattern
B. algorithmic test pattern
C. random test pattern
D. exhaustive test pattern
Answer: B
The algorithmic test pattern method uses the hardware finite state machine for generating algorithmic test vectors for the circuit under test.
19. A n-bit counter produces ______ number of total input combinations.
A. 2(n-1)
B. 2(n+1)
C. 2n
D. 2n
Answer: C
An n-bit counter produces a total of 2n number of all possible input combinations for testing the circuit under test and it is called an exhaustive test pattern method.
20. Exhaustive test pattern determines
A. gate-level faults
B. logic level faults
C. functional faults
D. structural faults
Answer: A
The exhaustive test pattern method detects all gate level struck-at fault and also bridging fault.
21. Exhaustive test pattern also detects delay faults.
A. true
B. false
Answer: B
The exhaustive test pattern method does not detect all transistor-level faults or delay faults since those faults need specific ordering.
22. Which is not suitable for circuits having large N values?
A. exhaustive test pattern method
B. pseudo-exhaustive test pattern method
C. random test pattern method
D. deterministic test pattern method
Answer: A
The exhaustive test pattern method is not suitable for circuits having large N values since there is a limit for fault coverage.
23. Which method needs fault simulation?
A. exhaustive test pattern method
B. pseudo-exhaustive test pattern method
C. random test pattern method
D. deterministic test pattern method
Answer: A
The exhaustive test pattern method needs fault simulation for determining fault coverage whereas the pseudo-exhaustive test pattern method does not need fault simulation.
24. In which method sequences are repeatable?
A. exhaustive test pattern method
B. pseudo-exhaustive test pattern method
C. random test pattern method
D. pseudo-random test pattern method
Answer: D
Pseudo-random test pattern method has properties similar to a random pattern sequence but the sequence is repeatable.
25. Which method is used for external functional testing?
A. exhaustive test pattern method
B. pseudo-exhaustive test pattern method
C. random test pattern method
D. pseudo-random test pattern method
Answer: C
The random test pattern method is used for external functional testing of microprocessors as well as in ATPG software.
26. Cells must be non-stackable in RAM storage cell.
A. true
B. false
Answer: B
Cells must be stackable, both side by side and from top to bottom. This must be carefully considered when the layout is made.
27. Which cell is non-volatile?
A. one-transistor dynamic cell
B. two-transistor dynamic cell
C. four transistor dynamic cell
D. pseudo static RAM cell
Answer: D
Pseudo-static RAM cell is a non-volatile cell. It is used for long time storage. Non-volatile memory is also called long-term memory.
28. In RAM arrays, the transistor is of
A. minimum size
B. maximum size
C. of any size
D. size doesn’t play a role
Answer: A
In RAM arrays, the transistor is of minimum size and thus it is incapable of sinking large charges quickly.
29. Which implementation is slower?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: B
NOR gate implementation is slower even though both NAND and NOR gate implementation are suitable for CMOS.
