# IC Chip Circuit Complexity MCQ [Free PDF] – Objective Question Answer for IC Chip Circuit Complexity Quiz

1. How many gates per chip are used in first-generation Integrated Circuits?

A. 3-30
B. 30-300
C. 300-3000
D. More than 3000

The first generation ICs belongs to small-scale integration, which consists of 3-30 gates per chip (approximately).

2. Find the chip area for a Medium Scale Integration IC?

A. 8 mm3
B. 4 mm2
C. 64 mm3
D. 16 mm2

The approximate length and breadth of Medium Scale Integration would be 4 mm. Therefore, its area is given as = length × breadth = 4mm × 4mm = 16mm2.

3. The number of transistors used in Very Large Scale Integration is

A. 107 transistors/chip
B. 106 – 107 transistors/chip
C. 203 – 105 transistors/chip
D. 102 – 203 transistors/chip

Very Large Scale Integration (VLSI) ICs are fabricated using more than 3000 gates/chip, which is equivalent to 20,000 – 1,00,00,00 transistors/chip.

4. What type of integration is chosen to fabricate Integrated Circuits like Counters, multiplexers, and Adders?

A. Small Scale Integration (SSI)
B. Medium Scale Integration (MSI)
C. Large Scale Integration (LSI)
D. Very Large Scale Integration (VLSI)

Fabrication of ICs like counters, multiplexers, and Adders requires 30-300 gates per chip. Therefore, Medium Scale Integration is best suitable.

5. Determine the chip area for Large Scale Integration ICs.

A. 1,00,000 mil2
B. 10,000 mil2
C. 1,60,000 mil2
D. 16,000 mil2

The chip area for a Large Scale Integration IC is 1 cm2.

=> Area of LSI = 10mm × 10mm = 1cm × 1 cm = 1cm2.

=> 1,60,000mil2 (1cm=400mil).

6. Ultra Large Scale Integration is used in the fabrication of

A. 8-bit microprocessors, RAM, ROM
B. 16 and 32- bit microprocessors
C. Special processors and Smart sensors
D. All of the mentioned

Ultra Large Scale Integration has nearly 106 – 107 transistors/chip. Hence, it is possible to fabricate smart sensors and a special processor.

7. The concept of Integrated circuits was introduced at the beginning of 1960 by

A. Texas instrument and Fairchild Semiconductor
B. Bell telephone laboratories and Fair child Semiconductor
C. Fairchild Semiconductor
D. Texas instrument and Bell telephone Laboratories

The concept of Integrated circuits was introduced by Texas instrument and Fairchild Semiconductor, whereas Bell telephone laboratories developed the concept of transistors.

8. Which process is used to produce small circuits of micron range on silicon wafer?

A. Photo etching
B. Coordinatograph
C. Photolithography
D. Ion implantation

It is possible to fabricate as many as 10,000 transistors on a 1cmX1cm chip, using a photolithography process.

9. Mention the technique used in the photolithography process

A. X-ray lithographic technique
B. Ultraviolet lithographic technique
C. Electron beam lithographic technique
D. All of the mentioned

All these techniques are used to produce device dimensions as small as 2µm or even down to the sub-micron range (<1µm).

10. Find the basic chemical reaction used for Epitaxial growth?

A. Sic4 + 4H ↔ Si + 4Hcl

B. Sic2 + H2 ↔ Si + 2Hcl

C. Sic4 + H2 ↔ Si + 4Hcl

D. 2Sic2 + 2H2 ↔ 4Si + Hcl

The basic chemical reaction used for epitaxial growth of pure silicon is the hydrogen reduction of silicon tetrachloride i.e Sic4 + H2 ↔ Si + 4Hcl

11. Which component is added to the p-type material in order to get the impurity concentration in epitaxial films?

A. Bi-borane (B2H2)
B. Phosphine (PH3)
C. Boron chloride (BCl3)
D. Phosphorous pentoxide (P2O5)

Bi-Borane is used for doping p-type materials and Phosphine is used for doping n-type materials whereas Boron chloride and Phosphorous pentoxide are used for doping during the diffusion process.

12. Where are the silicon wafers placed in the reaction chamber for the epitaxial growth process?

A. Cup
B. Boats
C. Ingots
D. Crucible

The silicon rods are not directly placed in the reaction chamber instead they are placed on a rectangular graphite rod called boats and then it is heated to 1200oc.

13. Which of the following is used to obtain silicon crystal structure while fabricating Integrating Circuits?

A. Oxidation
B. Epitaxial growth
C. Photolithography
D. Silicon wafer preparations

Epitaxial growth is the arranging of atoms in a single-crystal fashion upon a single crystal substrate so that the resulting layer is an extension of the substrate crystal structure.

14. Why oxidation process is required?

A. To protect against contamination
B. To use it for fabrication of various components
C. To prevent diffusion of impurities
D. All of the mentioned

Oxidation provides an extremely hard protective coating, thus protecting against contamination, and by selective etching, it can be made to fabricate components.

15. Mention the chemical reaction for oxidation process

A. Si + 2H2O –> SiO2 + 2H2
B. Si + O2 –> SiO2
C. 2Si + 2H2O –> 2SiO2 + 2H2
D. 2Si + 2H2O + 2O2 –> 2SiO2 + 2H2 + O2

For the oxidation process, silicon wafers are heated to a high temperature, and simultaneously they are exposed to a gas containing H2O or O2 or both.

16. At what temperature should the oxidation process be carried out to get an oxide film of thickness 0.02 to 2µm?

A. 0-105oc
B. 950-1115oc
C. 200-850oc
D. 350-900oc

Silicon wafers are raised to a high temperature in the range 950-1115oc and are exposed to the gas. The thickness of the layer is governed by time, temperature, and moisture content.

17. Oxidation process in silicon planar technology is also called as

A. Photooxidation
B. Silicon oxidation
C. Vapour oxidation
D. Thermal oxidation

The oxidation process is called the thermal oxidation process because high temperature is used to grow the oxide layer.

18. In the Crzochralski crystal growth process, the materials are heated up to

A. 950oc
B. 1000 oc
C. 1420oc
D. 1200oc

The materials are heated above 1420oc which is greater than the silicon melting point.

19. How to obtain silicon ingots of 10-15cm diameter?

A. By crystal pulling process
B. By crystal melting process
C. By crystal growing process
D. All of the mentioned

During the crystal pulling process, the seed crystal and the crucible rotate in opposite directions, in order to produce ingots of circular cross-section (diameter of 10/15cm normally obtained.

20. If the thickness of the wafer after all polishing steps in silicon wafer preparation is 23-40 mils. Find its raw cut slice thickness?

A. 16-32 mils
B. 23-40 mils
C. 8-12 mils
D. None of the mentioned

Usually, the silicon wafer obtained has a very rough surface due to the slicing operation. So, these wafers undergo a number of polishing steps to produce a flat and smooth polished surface. Therefore, the thickness of wafers will be reduced from its raw cut slice.

21. The process involved in photolithography is

A. Making of a photographic mask only
B. Photo etching
C. Both photo etching and the making of the photographic mask
D. None of the mentioned

Photolithography involves both processes in sequence. The first photographic mask is used for artwork and reduction. Then Photo etching for removal of SiO2 from the designed region.

22. How will be the initial artwork done for a normal IC?

A. Smaller than the final dimension of chip
B. Same as that of final dimension of chip
C. Larger than the final dimension of chip
D. None of the mentioned

The initial artwork of an IC is done at a scale several hundred times longer than the final dimensions. This is because, for a tiny chip, the larger the artwork, the more accurate is the final mask.

23. Find the area of artwork done for a monolithic chip of area 30mil × 30mil.

A. 16 cm × 16 cm
B. 60 cm × 60 cm
C. 12 cm × 12 cm
D. 36 cm × 36 cm

Drawings are magnified by a factor 500.
=> 1mil = 25µm
Therefore, 500mil = 1.2cm.

In an area of 30mil × 30mil, the area for artwork required

= 30mil × 1.2cm = 36cm × 36cm.

24. Mylar coated with a sheet of red photographic Mylar is used for artwork (layout) because,

A. It is used to get a colorful layout
B. It can be easily peeled off from the layout
C. It is recommended color for layouts
D. It is used for highlighting layout