1. Which of the following language can describe the hardware?
2. What do VHDL stand for?
A. Verilog hardware description language
B. VHSIC hardware description language
C. very hardware description language
D. VMEbus description language
3. What does VHSIC stand for?
A. very high speed integrated chip
B. very high sensor integrated chip
C. Verilog system integrated chip
D. Verilog speed integrated chip
4. Each unit to be modelled in a VHDL design is known as
A. behavioural model
B. design architecture
C. design entity
D. structural model
5. Which of the following are capable of displaying output signal waveforms resulting from stimuli applied to the inputs?
A. VHDL simulator
B. VHDL emulator
C. VHDL debugger
D. VHDL locater
6. Which of the following describes the connections between the entity port and the local component?
A. port map
B. one-to-one map
C. many-to-one map
D. one-to-many maps
7. Who proposed the CSA theory?
8. Which of the following is a systematic way of building up value sets?
A. CSA theory
B. Bayes theorem
C. Russell’s power mode;
D. first power model
9. Which of the following is an abstraction of the signal impedance?
10. Which of the following is an abstraction of the signal voltage?