Levels of Hardware Modelling MCQ Quiz – Objective Question with Answer for Levels of Hardware Modelling

11. Which model is used for the power estimation?

A. gate-level model
B. layout model
C. circuit model
D. switch model

Answer: A

The gate-level model is used to denote the boolean functions and the simulation only considers the behaviour of the gate. This model is also useful in power estimation since it provides accurate information about the signal transition probabilities.


12. In which model, the effect of instruction is simulated and their timing is not considered?

A. gate-level model
B. circuit model
C. coarse-grained model
D. layout model

Answer: C

The coarse-grained model is a kind of instruction set level modelling in which only the effect of instruction is simulated and the timing is not considered. The information which is provided in the manual is sufficient for this type of modelling.


13. Which models communicate between the components?

A. transaction-level modelling
B. fine-grained modelling
C. coarse-grained modelling
D. circuit level model

Answer: A

The transaction-level modelling is a type of instruction set level model. This modelling helps in the modelling of components which is used for communication purpose. It also models the transaction, such as read and write cycles.


14. Which of the following has a cycle-true set of simulations?

A. switch-level model
B. layout model
C. circuit-level
D. fine-grained model

Answer: D

The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the exact number of clock cycles which is required to run an application.


15. Which of the following language can describe the hardware?

A. C
B. C++

Answer: D

The VHDL is the hardware description language which describes the hardware whereas the C, C++ and JAVA are software languages.


16. What do VHDL stand for?

A. Verilog hardware description language
B. VHSIC hardware description language
C. very hardware description language
D. VMEbus description language

Answer: B

VHDL is the VHSIC(very high speed integrated circuit) hardware description language which was developed by three companies, IBM, Intermetrics and Texas Instruments the first version of the VHDL is established in the year 1984 and later on the VHDL is standardised by the IEEE.


17. What does VHSIC stand for?

A. very high speed integrated chip
B. very high sensor integrated chip
C. Verilog system integrated chip
D. Verilog speed integrated chip

Answer: A

The VHSIC stands for very high speed integrated chip and VHDL was designed in the context of the VHSIC, developed by the department of defence in the US.


18. Each unit to be modelled in a VHDL design is known as

A. behavioural model
B. design architecture
C. design entity
D. structural model

Answer: C

Each unit to be modelled in a VHDL design is known as the design entity or the VHDL entity. There are two types of ingredients are used. These are the entity declaration and the architecture declaration.


19. Which of the following are capable of displaying output signal waveforms resulting from stimuli applied to the inputs?

A. VHDL simulator
B. VHDL emulator
C. VHDL debugger
D. VHDL locater

Answer: A

The VHDL simulator is capable of displaying the output signal waveforms which result from the stimuli or trigger applied to the input.


20. Which of the following describes the connections between the entity port and the local component?

A. port map
B. one-to-one map
C. many-to-one map
D. one-to-many maps

Answer: A

The port map describes the connection between the entity port and the local component. The component is declared by component declaration and the entity ports are mapped with the port mapping.

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