Electrical Properties of MOS and BiCMOS Circuits MCQ Quiz – Objective Question with Answer for Electrical Properties of MOS and BiCMOS Circuits MCQ MCQ
A. incident radiation
B. reflected radiation
C. etching
D. diffracted radiation
Answer: A
Latch-up can be induced by glitches on the supply rail or by incident radiation.
72. How many transistors might bring up a latch-up effect in the p-well structure?
A. two
B. three
C. one
D. four
Answer: A
Two transistors and two resistances might bring up the latch-up effect in the p-well structure. These are associated with p-well and with regions of the substrate.
73. Substrate doping level should be decreased to avoid the latch-up effect.
A. true
B. false
Answer: B
An increase in substrate doping level with a consequent drop in the value of Rs can be used as a remedy for the latch-up problem.
74. What can be introduced to reduce the latch-up effect?
A. latch-up rings
B. guard rings
C. latch guard rings
D. substrate rings
Answer: B
The introduction of guard rings can reduce the effect of the latch-up problem. Guard rings are diffusions that decouple the parasitic bipolar transistors.
75. Which process produces a circuit that is less prone to the latch-up effect?
A. CMOS
B. nMOS
C. pMOS
D. BiCMOS
Answer: D
BiCMOS process produces circuits that are less likely to suffer from latch-up problems whereas CMOS circuits are very highly prone to latch-up problems.
76. Which one of the following is the main factor for reducing the latch-up effect?
A. reduced p-well resistance
B. reduced n-well resistance
C. increased n-well resistance
D. increased p-well resistance
Answer: B
One of the main factors in reducing the latch-up effect is reduced n-well resistance Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and a higher value of holding current is also required.
77. The parasitic PNP transistor has the effect of _______ carrier lifetime.
A. increasing
B. decreasing
C. exponentially decreasing
D. exponentially increasing
Answer: B
The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region.
78. The reduction in carrier lifetime brings about __________
A. reduction in alpha
B. reduction in beta
C. reduction in current
D. reduction in voltage
Answer: B
The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.
79. To reduce the latch-up effect substrate resistance should be high.
A. true
B. false
Answer: B
To reduce the latch-up effect, substrate resistance Rs should be low. The reduction of Rs and Rw means that a larger lateral current is necessary to invite a latch-up.
80. Latch-up is the generation of __________
A. low impedance path
B. high impedance path
C. low resistance path
D. high resistance path
Answer: A
Latch-up is the generation of the low-impedance path in CMOS chips between the power supply and ground rails.
