1. What is Lithography?
A. Process used to transfer a pattern to a layer on the chip
B. Process used to develop an oxidation layer on the chip
C. Process used to develop a metal layer on the chip
D. Process used to produce the chip
Answer: A
Lithography is the process used to develop a pattern to a layer on the chip.
2. Silicon oxide is patterned on a substrate using ____________
A. Physical lithography
B. Photolithography
C. Chemical lithography
D. Mechanical lithography
Answer: B
Silicon oxide is patterned on a substrate using Photolithography.
3. Positive photo resists are used more than negative photo resists because ___________
A. Negative photoresists are more sensitive to light, but their photolithographic resolution is not as high as that of the positive photoresists
B. Positive photoresists are more sensitive to light, but their photolithographic resolution is not as high as that of the negative photoresists
C. Negative photoresists are less sensitive to light
D. Positive photoresists are less sensitive to light
Answer: A
Negative photoresists are more sensitive to light, but their photolithographic resolution is not as high as that of the positive photoresists. Therefore, negative photoresists are used less commonly in the manufacturing of high-density integrated circuits.
4. The ______ is used to reduce the resistivity of polysilicon.
A. Photoresist
B. Etching
C. Doping impurities
D. None of the mentioned
Answer: C
The resistivity of polysilicon is reduced by Doping impurities.
5. The isolated active areas are created by a technique known as ___________
A. Etched field-oxide isolation
B. Local Oxidation of Silicon
C. Etched field-oxide isolation or Local Oxidation of Silicon
D. None of the mentioned
Answer: C
To create isolated active areas both techniques can be used. Among them, Local Oxidation of Silicon(LOCOS) is the most efficient.
6. The chemical used for shielding the active areas to achieve selective oxide growth is?
A. Silver Nitride
B. Silicon Nitride
C. Hydrofluoric acid
D. Polysilicon
Answer: B
Selective oxide growth is achieved by shielding the active areas. Silicon nitride (Si3N4) is used for shielding the active areas during oxidation, which effectively inhibits oxide growth.
7. The dopants are introduced in the active areas of silicon by using which process?
A. Diffusion process
B. Ion Implantation process
C. Chemical Vapour Deposition
D. Either Diffusion or Ion Implantation Process
Answer: D
Two ways to add dopants are diffusion and ion implantation.
8. To grow the polysilicon gate layer, which of the following chemical is used for chemical vapor deposition?
A. Silicon Nitride(Si3N4)
B. Silane gas(SiH4)
C. Silicon oxide
D. None of the mentioned
Answer: B
Silicon Wafer is placed in a reactor with silane gas (SiH4), and they are heated again to grow the polysilicon layer by chemical vapor deposition.
9. The process by which Aluminium is grown over the entire wafer, also filling the contact cuts is?
A. Sputtering
B. Chemical vapor deposition
C. Epitaxial growth
D. Ion Implantation
Answer: A
Aluminum is sputtered over the entire wafer, it also fills the contact cuts.
10. Chemical Mechanical Polishing is used to ___________
A. Remove silicon oxide
B. Remove silicon nitride and pad oxide
C. Remove the polysilicon gate layer
D. Reduce the size of the layout
Answer: B
The pad oxide and nitride are removed using a Chemical Mechanical Polishing (CMP) step.
11. What is Piranha Solution?
A. It is a 3:1 to 5:1 mix of nitric acid and hydrogen peroxide that is used to develop the oxide layer on a silicon substrate
B. It is a 3:1 to 5:1 mix of sulphuric acid and hydrofluoric acid that is used to clean silicon wafers removing organic and metal contaminants or photoresists after metal patterning
C. It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to grow the oxide layer on the silicon
D. It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to clean wafers of organic and metal contaminants or photoresists after metal patterning
Answer: D
Piranha solution is a 3:1 to 5:1 mix of sulfuric acid and hydrogen peroxide that is used to clean silicon wafers of metal and organic contaminants or photo-resist after metal patterning.
12. What are the advantages of BiCMOS?
A. higher gain
B. high-frequency characteristics
C. better noise characteristics
D. all of the mentioned
Answer: D
BiCMOS provides higher gain, better noise, and high-frequency characteristics than MOS transistors.
13. What are the features of BiCMOS?
A. low input impedance
B. high packing density
C. high input impedance
D. bidirectional
Answer: A
Some of the features of BiCMOS are low input impedance, low packing density, unidirectional, high output drive current, etc.
14. BiCMOS has low power dissipation.
A. true
B. false
Answer: B
BiCMOS has high power dissipation and CMOS has low power dissipation.
15. CMOS is __________
A. unidirectional
B. bidirectional
C. directional
D. none of the mentioned
Answer: A
BiCMOS is unidirectional and CMOS is bidirectional.
16. In bipolar transistor, its quality can be improved by __________
A. increasing collector resistance
B. decreasing collector resistance
C. collector resistance does not affect the quality
D. decreasing gate resistance
Answer: B
The quality of the bipolar transistor can be improved by reducing the collector resistance, which can be done by using the additional layer of n+ subcollector.
17. BiCMOS can be used in __________
A. amplifying circuit
B. driver circuits
C. divider circuit
D. multiplier circuit
Answer: B
BiCMOS is more advantageous and improved than CMOS and it can be used in I/O and driver circuits.
18. What are the advantages of E-beam masks?
A. small feature size
B. larger feature size
C. looser layer
D. complex design
Answer: A
The advantages of E-beam masks are it has a tighter layer to layer registration and it has smaller feature sizes.
19. Which process is used in E-beam machines?
A. raster scanning
B. vector scanning
C. raster & vector scanning
D. none of the mentioned
Answer: C
The two approaches to the design of E-beam machines are raster scanning and vector scanning.
20. What is the feature of vector scanning?
A. faster
B. slow
C. easy handling
D. very simple design
Answer: A
Vector scanning is faster but the data handling involved is more complex. Vector scanning is done between the endpoints.
21. Which has high input resistance?
A. nMOS
B. CMOS
C. pMOS
D. BiCMOS
Answer: B
CMOS technology has high input resistance and is best for constructing simple low-power logic gates.
22. BiCMOS has a lower standby leakage current.
A. true
B. false
Answer: B
BiCMOS has the potential for high standby leakage current and has high power consumption compared to CMOS.
23. CMOS technology is used in developing which of the following?
A. microprocessors
B. microcontrollers
C. digital logic circuits
D. all of the mentioned
Answer: D
CMOS technology is used in developing microcontrollers, microprocessors, digital logic circuits and other integrated circuits.
24. CMOS technology is used in developing which of the following?
A. microprocessors
B. microcontrollers
C. digital logic circuits
D. all of the mentioned
Answer: D
CMOS technology is used in developing microcontrollers, microprocessors, digital logic circuits, and other integrated circuits.
25. CMOS has __________
A. high noise margin
B. high packing density
C. high power dissipation
D. high complexity
Answer: B
Some of the properties of CMOS are that it has low power dissipation, high packing density and low noise margin.
26. In CMOS fabrication, nMOS and pMOS are integrated in the same substrate.
A. true
B. false
Answer: A
In CMOS fabrication, nMOS and pMOS are integrated into the same chip substrate. n-type and p-type devices are formed in the same structure.
27. P-well is created on __________
A. p substrate
B. n substrate
C. p & n substrate
D. none of the mentioned
Answer: B
P-well is created on n substrate to accommodate n-type devices whereas p-type devices are formed in the N-type substrate.