1. nMOS fabrication process is carried out in ____________
A. thin wafer of a single crystal
B. thin wafer of multiple crystals
C. thick wafer of a single crystal
D. thick wafer of multiple crystals
Answer: A
The nMOS fabrication process is carried out in a thin wafer of a single crystal with high purity.
2. ______________ impurities are added to the wafer of the crystal.
A. n impurities
B. p impurities
C. silicon
D. crystal
Answer: B
p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.
3. What kind of substrate is provided above the barrier to dopants?
A. insulating
B. conducting
C. silicon
D. semiconducting
Answer: A
Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned.
4. The photoresist layer is exposed to ____________
A. Visible light
B. Ultraviolet light
C. Infra red light
D. LED
Answer: B
The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.
5. In nMOS device, gate material could be ____________
A. silicon
B. polysilicon
C. boron
D. phosphorus
Answer: B
In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.
6. Which is the commonly used bulk substrate in nMOS fabrication?
A. silicon crystal
B. silicon-on-sapphire
C. phosphorus
D. silicon-di-oxide
Answer: C
In nMOS fabrication, the bulk substrate used can be either bulk silicon or silicon-on-sapphire.
7. In nMOS fabrication, etching is done using ____________
A. plasma
B. hydrochloric acid
C. sulphuric acid
D. sodium chloride
Answer: A
In nMOS fabrication, etching is done using hydrofluoric acid or plasma. Etching is a process used to remove layers from the surface.
8. Heavily doped polysilicon is deposited using ____________
A. chemical vapour decomposition
B. chemical vapour deposition
C. chemical deposition
D. dry deposition
Answer: B
The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition.
9. In diffusion process ______ impurity is desired.
A. n type
B. p type
C. np type
D. none of the mentioned
Answer: A
Diffusion is carried out by heating the wafer to high temperature and passing a gas containing the desired ntype impurity.
10. Contact cuts are made in ____________
A. source
B. drain
C. metal layer
D. diffusion layer
Answer: A
Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where a connection has to be made.
11. Interconnection pattern is made on ____________
A. polysilicon layer
B. silicon-di-oxide layer
C. metal layer
D. diffusion layer
Answer: C
The metal layer is masked and etched to form an interconnection pattern. The metal layer was formed using aluminium deposited over the formed surface.
12. SIlicon-di-oxide is a good insulator.
A. true
B. false
Answer: A
SIlicon-di-oxide is a very good insulator so a very thin layer is required in the fabrication of MOS transistor.
13. _______ is used to suppress unwanted conduction.
A. phosphorus
B. boron
C. silicon
D. oxygen
Answer: B
Boron is used to suppressing the unwanted conduction between transistor sites. It is implanted in the exposed regions.
14. Which is used for the interconnection?
A. boron
B. oxygen
C. aluminium
D. silicon
Answer: C
Aluminium is the suitable material used for the circuit interconnection or connecting two layers.
15. CMOS technology is used in developing which of the following?
A. microprocessors
B. microcontrollers
C. digital logic circuits
D. all of the mentioned
Answer: D
CMOS technology is used in developing microcontrollers, microprocessors, digital logic circuits and other integrated circuits.
16. CMOS technology is used in developing which of the following?
A. microprocessors
B. microcontrollers
C. digital logic circuits
D. all of the mentioned
Answer: D
CMOS technology is used in developing microcontrollers, microprocessors, digital logic circuits and other integrated circuits.
17. CMOS has __________
A. high noise margin
B. high packing density
C. high power dissipation
D. high complexity
Answer: B
Some of the properties of CMOS are that it has low power dissipation, high packing density and low noise margin.
18. In CMOS fabrication, nMOS and pMOS are integrated in same substrate.
A. true
B. false
Answer: A
In CMOS fabrication, nMOS and pMOS are integrated in the same chip substrate. n-type and p-type devices are formed in the same structure.
19. P-well is created on __________
A. p substrate
B. n substrate
C. p & n substrate
D. none of the mentioned
Answer: B
P-well is created on n substrate to accommodate n-type devices whereas p-type devices are formed in the ntype substrate.
20. Oxidation process is carried out using __________
A. hydrogen
B. low purity oxygen
C. sulphur
D. nitrogen
Answer: A
The oxidation process is carried out using high purity oxygen and hydrogen. Oxidation is the process of oxidizing or being oxidised.
21. Photoresist layer is formed using __________
A. high sensitive polymer
B. light-sensitive polymer
C. polysilicon
D. silicon dioxide
Answer: B
Light sensitive polymer is used to form the photoresist layer. The photoresist is a light-sensitive material used to form a patterned coating on a surface.
22. In CMOS fabrication, the photoresist layer is exposed to __________
A. visible light
B. ultraviolet light
C. infrared light
D. fluorescent
Answer: B
The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.
23. Few parts of photoresist layer is removed by using __________
A. acidic solution
B. neutral solution
C. pure water
D. diluted water
Answer: A
Few parts of the photoresist layer is removed by treating the wafer with a basic or acidic solution. Acidic solutions are those which have a pH less than 7 and basic solutions have greater than 7.
24. P-well doping concentration and depth will affect the __________
A. threshold voltage
B. Vss
C. Vdd
D. Vgs
Answer: A
Diffusion should be carried out very carefully, as doping concentration and depth will affect both threshold voltage and breakdown voltage.
25. Which type of CMOS circuits are good and better?
A. p well
B. n well
C. all of the mentioned
D. none of the mentioned
Answer: B
N-well CMOS circuits are better than p-well CMOS circuits because of the lower substrate bias effect.
26. N-well is formed by __________
A. decomposition
B. diffusion
C. dispersion
D. filtering
Answer: B
N-well is formed by using ion implantation or diffusion. Ion implantation is a process by which ions of a material are accelerated in an electrical field and impacted into a solid. Diffusion is a process in which the net movement of ions or molecules plays a major role.
27. _______ is sputtered on the whole wafer.
A. silicon
B. calcium
C. potassium
D. aluminium
Answer: D
Aluminium is sputtered on the whole wafer before removing the excess metal from the wafer.