21. For improved base current discharge ________ enhancement type nMOS devices have to be added.
A. two
B. three
C. one
D. four
22. The BJTs in the BICMOS circuit is in _____________ configuration.
A. Push-pull
B. Totem pole
C. Active high
D. Active low
23. The MOSFETS are arranged in this configuration to provide __________
A. Zero static power dissipation
B. High Input impedance
C. Both zero static power dissipation and high input impedance
D. None of the mentioned
24. In latch-up condition, parasitic component gives rise to __________ conducting path.
A. low resistance
B. high resistance
C. low capacitance
D. high capacitance
25. Latch-up can be induced by __________
A. incident radiation
B. reflected radiation
C. etching
D. diffracted radiation
26. How many transistors might bring up a latch-up effect in the p-well structure?
A. two
B. three
C. one
D. four