# Practical Aspects and Testability of VLSI MCQ Quiz – Objective Question with Answer Practical Aspects and Testability for

1. Reduction in power dissipation can be brought by

A. increasing transistor area
B. decreasing transistor area
C. increasing transistor feature size
D. decreasing transistor feature size

The 3:1 reduction in power dissipation can be brought at the expense of increasing the transistor area by 50%.

2. When does the longest delay occur in 8:1 inverters?

A. during 1 to 0 transition
B. during 0 to 1 transition
C. during faster speed
D. delays are always short

In 8:1 inverters, the longest delay will occur when the output of the first stage is changing from logic 0 to 1 and capacitance must charge through pull-up resistance.

3. In inverter during logic 1 to 0 transition, capacitance discharges at

A. pull-up resistance
B. pull-down resistance
C. both pull-up and pull-down
D. at gate

During the logic 1 to 0 transition, the capacitance which is charged through pull-up must always discharge through the pull-down transistor at the first stage.

4. In minimum size nMOS 8:1 inverter, the logic 0 to 1 transition delay is given as

A. 5Ʈ
B. 20Ʈ
C. 40Ʈ
D. 50Ʈ

For minimum pull-down feature size nMOS 8:1 inverter, the logic 0 to 1 transition delay can be given as 8Rs × 5 square Cg which gives 40Ʈ.

5. In minimum size nMOS 8:1 inverter, the logic 1 to 0 transition delay is given as

A. 5Ʈ
B. 20Ʈ
C. 40Ʈ
D. 50Ʈ

8:1 nMOS inverter allows stray and wiring capacitance and the logic 1 to 0 transition delay can be given as 1Rs x 5 square Cg which gives 5Ʈ.

6. For a regular 8:1 inverter, the transition delay is given as

A. 10Ʈ
B. 20Ʈ
C. 21Ʈ
D. 25Ʈ

For the 8:1 inverter, the logic 0 to 1 transition delay can be given as 21Ʈ and logic 1 to 0 transition delay can be given as 2(1/3)Ʈ.

7. The area of the CMOS inverter is proportional to

A. area of n device
B. area of p device
C. total area of n and p device
D. square of minimum feature size

The area of a basic CMOS inverter is proportional to the total area occupied by the p and n devices (WpLp + WnLn).

8. The ratio of Wp/Wn can be given as

A. 1:2
B. 2:1
C. 1:1
D. 2:2

The minimum area can be achieved by choosing minimum dimensions for Wp, Wn, Lp, Ln which is 2λ and the ratio of Wp/Wn can be given as 1:1.

9. Switching power dissipation can be given as

A. Cl × Vdd × f
B. Vdd2 × f
C. Cl × Vdd2
D. Cl × Vdd2 × f

Switching power dissipation Psd can be given as Cl x Vdd2 x f where Cl is load capacitance, Vdd is the power supply voltage and f is the frequency of switching.

10. Load capacitance can be minimized by

A. increasing A
B. decreasing A
C. increasing Psd
D. does not depend on A

For fixed Vdd and f, minimizing Psd requires minimizing Cl which can be minimized by decreasing area A as it is directly proportional to gate area.

11. Rise time and fall time can be equalized by

A. βn = βp
B. βn = 2βp
C. βp = 2βn
D. βn = 1/2βp

Rise time tr and fall time tf can be equalized by using βn = βp, which requires (Wp/Lp) = (µn/µp)(Wn/Ln).

12. Rise time and fall time can be also equalized by

A. Lp = Ln = λ
B. Lp = Ln = λ/2
C. Lp = Ln = 2λ
D. 2Lp = Ln = λ

Rise time and fall time can be equalized by taking Lp = Ln = 2λ which implies Wp/Wn = 2 and also µn/µp = 2.

13. Equalizing of rise time and the fall time is possible in

A. nMOS
B. pseudo nMOS
C. CMOS
D. pMOS

Equalizing of rise time and fall time is possible only in CMOS and not possible in nMOS and pseudo nMOS because of the ratio requirement.

14. High and low noise margins can be equalized by

A. βn = βp
B. βn greater than βp
C. βn lesser than βp
D. Lp = 2Ln

High and low noise margins can be equalized by choosing βn = βp, also Ln = Lp which implies Wp/Wn = 2.

15. Inverter pair delay D is given as equal to

A. tr
B. tf
C. tr-tf
D. tr+tf

Inverter pair delay D is given as the sum of rise time and fall time. This is proportional to (Rp+Rn)Cl where Rp and Rn are average resistances.

16. For minimum D consider

A. Ln = Lp = 2λ
B. Ln greater than Lp = 2λ
C. Lp greater than Ln
D. Lp = 2Ln

D increases with Ln and Lp so for minimum D we have to choose Ln=Lp=2λ. D does not vary significantly with (1) lesser than (Wn/Wp) lesser than (2).

17. Different parameter optimization is easily achievable in

A. nMOS
B. pMOS
C. pseudo nMOS
D. CMOS

Different parameter optimizations like noise margins equalization, rise time fall time equalization can be easily achievable in CMOS.

18. Minimizing A with respect to Wp.d. gives

A. Wp.d. = 2λ
B. Wp.d. = λ/2
C. Wp.d. = (k)1/2 × 2λ
D. Wp.d. = k × (λ)1/2 × 2

Minimizing A with respect to Wp.d yields a solution as Wp.d. = (k)1/2 × Wp.u. = (k)1/2 × 2λ.

19. Using Zp.u./Zp.d = k, Lp.u. can be obtained as

A. k × 2λ
B. k × λ
C. (k)1/2 × 2λ
D. k × 2 × (λ)1/2

Using this ratio Zp.u./Zp.d. = k, we obtain Lp.u. = (k)1/2 × Lp.d. = (k)1/2 × 2λ.

20. Minimum area can be given as

A. 4 × Ao × λ × (k)1/2
B. 4 × Ao × λ × k
C. 8 × Ao × λ2 × (k)1/2
D. 8 × Ao × λ × (k)1/2

Minimum area A can be given as 8 x Ao x λ2 x (k)1/2 which implies Zp.u. = (k)1/2 and Zp.d. = 1/(k)1/2.

21. When Zp.d. or Zp.u. increases, delay

A. increases
B. decreases
C. remains the same
D. delay becomes zero

Pd is minimized by increasing Zp.d. Large Zp.d. requires large Zp.u. which results in an increase in delay D of the inverter pair.

22. For minimum D which relation is chosen?

A. Zp.u. = 1/2k
B. Zp.u. = k
C. Zp.d. = 1/k
D. Zp.d. = 1

For minimum D, Zp.u. is 1 and Zp.d. is equal to 1/k with Wp.u. = 2λ and Wp.d. = k × 2λ.

23. Noise margin measures the changing strength of

A. input voltage
B. output voltage
C. threshold voltage
D. supply voltage

Noise margin measures by how much the input voltage can change without disturbing the present logic output state.

24. Which has better noise margins?

A. nMOS
B. pMOS
C. CMOS
D. BiCMOS

CMOS has better noise margins than nMOS especially at low conditions because ratio adjustment is easier in CMOS.

25. A 4-bit processor has two buses which are

A. unidirectional
B. bidirectional
C. one unidirectional and one bidirectional
D. more than two buses

A 4-bit processor has two buses one is bidirectional to carry operand and output to shifter and register array and another bus is unidirectional to carry input.

26. The IN and OUT bus lines relative positions are interchanged to

A. match height
B. match length
C. match width
D. match thickness

The IN and OUT bus line’s relative positions are interchanged to make the cell stretchable and to match the height of the block and spacings.

27. The IN and OUT bus lines should be in

A. metal
B. polysilicon
C. diffusion
D. silicon

The IN and OUT bus lines should be in metal rather than diffusion or polysilicon to mate with the bus structures of other blocks.

28. Extensions are

A. vertical
B. horizontal
C. diagonal
D. haphazard

Extensions are horizontal or parallel to the stratified unit and rifts are described as extension zones.

29. Rifts and extensions should be placed in

A. The minimum amount of geometry
B. The maximum amount of geometry
C. in slopes
D. anywhere in the layout

Rifts and extensions should be placed where they cut a minimum amount of simple geometry, one in polysilicon and one in diffusion.

30. Rifts are used for smooth flow through buses.

A. true
B. false

Rifts are used for smooth flow through buses as suggested and hence one is used in polysilicon and the other in diffusion.

A. polysilicon
B. metal
C. silicon
D. carbon

Input and output pads are made up of metal and it used to connect chips from one circuitry to another.

A. in the chip
B. exactly at the center of the chip
C. edge of the chip
D. above the chip

Bonding pads are positioned near the edge of the chips although there will be a Vdd bus between bonding pads and the chip boundary.

33. Which pad contains Schmitt trigger circuitry?

The input pad contains overvoltage protection features and also contains inverting circuitry or Schmitt trigger circuitry.

34. Which occupies a lesser area?

Output pads provide a large current for off-wiring and also inputs to other devices. But these pads use minimum space.

35. Buffers are needed to drive

A. small capacitance
B. large capacitance
C. small resistance
D. large resistance

Buffers are necessary for environments on and off-chip. It is used to drive relatively large capacitances associated with circuits of the chip.

36. Pads must be placed generally in the periphery of the chip area.

A. true
B. false

Usually, pads must be placed in the periphery of the chip area otherwise bonding difficulties may be encountered.

37. How much area should be allocated for pads?

A. one third
B. two-third
C. half
D. three fourth

According to a thumb rule, the small system designer should allow one-third of the chip area for pads.

38. Which provides large capacitance?

B. bus wiring capacitance
C. sheet capacitance
D. area capacitance

Bus wiring capacitance Cbus provides the largest capacitance for a typical bus system for example for small chips this can be as high as 0.8pF.

39. Bus wiring capacitance is driven through

A. one transistor
B. two transistors
C. three transistors
D. no transistors

Bus wiring capacitance is driven through pull-up and pull-down transistors and through at least one pass transistor or transmission gate in the series.

40. What is the delay of input pads?

A. 5Ʈ
B. 10Ʈ
C. 40Ʈ
D. 30Ʈ

The input pad always contains overvoltage protection circuitry and Schmitt trigger circuitry. Its total delay is 30Ʈ.

41. The total delay for the select register circuit is

A. 33Ʈ
B. 60Ʈ
C. 55Ʈ
D. 73Ʈ

The total delay for the select register is 73Ʈ. It is the sum of delays of the input pad, three pass transistors, and driver inverter pair.

42. Delay for data propagation is

A. 10 nsec
B. 50 nsec
C. 100 nsec
D. 150 nsec

Data is propagated through the bus. The bus can be bidirectional but data can be propagated through the bus only in one direction at a time. The delay for this data propagation is 100 nsec.

43. Which is the longest delay in the adder process?

A. sum delay
B. carry delay
C. propagation delay
D. inverter delay

The longest delay in the adder process is the carry chain delay. This is the process of forming carry out which propagates through all bits of the adder.

44. The total delay for the adder process is

A. 100 nsec
B. 200 nsec
C. 220 nsec
D. 250 nsec

The total delay for the adder process is 220 nsec. The total delay is the sum of select register delays, bus delays, and carries chain delays.

45. The refreshing clock period should propagate through

A. memory cell
B. wiring
C. carry chain
D. any subunit

Clock 2 which is the refreshing clock should propagate through wiring and finite rise and fall time must be allowed.

46. The value of Ʈ for 5-micron technology is always constant.

A. true
B. false

The range of value of Ʈ for 5-micron technology was calculated to be 0.1 to 0.3 nsec but it may vary upto 0.6 nsec.

47. The total clock period for the adder process is

A. 100 nsec
B. 150 nsec
C. 200 nsec
D. 250 nsec

The total clock period of the adder process is 250 nsec which is the sum of all the delays (220 nseC. and the period of different phases of the process.

48. The Zp.u./Zp.d. ratio for the nMOS inverter is

A. 4:1
B. 3:1
C. 1:4
D. 1:3

For nMOS inverters, the Zp.u./Zp.d. ratio is 4:1 when driven from another inverter and 8:1 when driven through one or more pass transistors.

49. The impedance ratio for pseudo-nMOS is

A. 4:1
B. 3:1
C. 1:4
D. 1:3

For pseudo-nMOS, the Zp.u./Zp.d. ratio is 3:1 and for CMOS 1:1 ratio is required for the minimum area.

50. What is the value of peripheral capacitance for 5-micron technology?

A. 4 × 10(-4) pf/µm2
B. 5 × 10(-4) pf/µm2
C. 8 × 10(-4) pf/µm2
D. 12 × 10(-4) pf/µm2