A. gate to source capacitance
B. gate to drain capacitance
C. source to drain capacitance
D. gate to channel capacitance
Answer: D
1 square Cg is defined as the gate-to-channel capacitance of a MOS transistor having a standard feature size (W=L).
52. What is the delay value Ʈ for 1.2-micron technology?
A. 0.1 nsec
B. 0.12 nsec
C. 0.046 nsec
D. 0.064 nsec
Answer: C
The delay Ʈ is the time constant and for 1.2-micron technology its value is 0.046 nsec.
53. Which is used to increase Ʈ?
A. parasitic capacitance
B. peripheral capacitance
C. area capacitance
D. load capacitance
Answer: A
Circuit wiring and parasitic capacitance must be allowed to increase the value of Ʈ by the factor of 2 or 3.
54. The inverter pair delay is given by
A. (Zp.u./Zp.d.)Ʈ
B. (1+ Zp.u./Zp.d.)Ʈ
C. (1+ Zp.u./Zp.d.)Ʈ
D. (1+ Ʈ)Zp.u./Zp.d.
Answer: B
The inverter delay is given by (1+ Zp.u./Zp.d.)Ʈ. The inverter pair delay for CMOS is 7Ʈ.
55. The number of stages N is given by
A. ln(y)/ln(f)
B. ln(f)/ln(y)
C. ln(2y)/ln(f)
D. ln(y)/ln(2f)
Answer: A
To calculate the value for N, where N inverters are cascaded, each one of which is larger than the preceding stage by a width factor f the formula used is ln(y)/ln(f).
56. If f assumes the value e then delay is
A. maximized
B. minimized
C. does not change
D. doubled
Answer: B
Total delay is minimized if f assumes the value of e which is the base of the natural logarithm. This applies to both nMOS and CMOS.
57. Propagation delay is given by
A. nrcƮ
B. n2rcƮ
C. nr2cƮ
D. n2cƮ
Answer: B
Propagation delay through cascaded pass transistors or transmission gates can be given as n2rcƮ.
58. Using _____ long wires is possible.
A. silicide
B. metal
C. polysilicon
D. diffusion
Answer: A
Using silicide, reasonable long wires are possible. It is a modest RC product. Silicides are used in place of polysilicon in some nMOS processes.
59. One pass transistor can be driven through the output of another.
A. true
B. false
Answer: B
No pass transistor gate must be driven through the output of one or more pass transistors since logic 1 levels are degraded by the threshold voltage.
60. Pass transistors are allowed to be constructed under
A. diffusion layer
B. polysilicon layer
C. metal layer
D. silicon layer
Answer: C
Pass transistors are allowed to be constructed under metal layers to save space and be more convenient.
71. Maximum allowable current density in aluminum is
A. 0.1 mA/µm2
B. 0.5 mA/µm2
C. 2 mA/µm2
D. 1 mA/µm2
Answer: D
The maximum allowable current density in the aluminum wire is 1 mA/µm2. Otherwise, metal migration may occur.
72. In which design all circuitry and all interconnections are designed?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: A
Full custom design is the complete design for the implementation. It contains all circuitry and all interconnections/communication paths.
73. Which design contains only the interconnections designed?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: C
Gate array design which is also known as uncommitted logic array design has the design of only the interconnections/communication paths.
74. In which method regularity is used to reduce complexity?
A. random approach
B. hierarchical approach
C. algorithmic approach
D. semi-design approach
Answer: B
The hierarchical approach is the one in which principles of iteration or regularity can be used to reduce the complexity of the design task.
75. Size of the die is determined using
A. transistor size
B. inverter size
C. area of the circuitry
D. length of the circuitry
Answer: C
The size of the die is determined by the area occupied by the circuitry. Large die sizes are associated with poor yields and high costs.
76. Which design is faster?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: C
Gate array design is faster than a prototype full-custom design and the final custom designs must be carefully optimized.
77. Which has relatively low-level capabilities?
A. hand-crafted designs
B. computer-assisted textual entry
C. computer-assisted graphical entry
D. silicon compiler-based design
Answer: B
Computer-assisted textual entry has programs that may be relatively low-level capabilities and it allows the entry of rectangular boxes, wires, etc.
78. Computer-assisted graphical entry is done through
A. monochrome
B. grayscale graphics
C. bichrome
D. trichrome
Answer: A
Computer-assisted graphical entry of mask geometry is through either monochrome or color graphics terminal.
79. Which method is used for verification along with generation?
A. hand-crafted designs
B. computer-assisted textual entry
C. computer-assisted graphical entry
D. silicon compiler-based design
Answer: C
Computer-assisted graphical entry method encourages regularity and is generally used with a generate then verify design philosophy.
80. Which method uses a high-level programming language?
A. hand-crafted designs
B. computer-assisted textual entry
C. computer-assisted graphical entry
D. silicon compiler-based design
Answer: D
Silicon compiler-based design uses a high-level approach and uses special languages like high-level language compilers.
81. The set of design rules does not give
A. widths
B. spacing
C. colors
D. overlaps
Answer: C
Communication between the fabrication house and the designer takes the form of a set of design rules with gives clearance, widths, spacing, overlaps, etc.
82. Caltech intermediate form code is a
A. low-level graphic language
B. low-level textual language
C. high-level graphic language
D. high-level textual language
Answer: A
Caltech intermediate form code is a low-level graphic language used to specify the geometry of integrated circuits.
83. CIF generates code that is
A. high-level language
B. assembly level language
C. machine-readable language
D. very high-level language
Answer: C
CIF code is to communicate chip geometry in a standard machine-readable form for mask-making.
84. CIF code is compatible with
A. low system geometry
B. large system geometry
C. both low and large system geometry
D. medium system geometry
Answer: C
CIF code is reasonably compact and can cope with both low and large system geometry. It is easily readable.
85. Design through CIF is done using
A. color codes
B. geometric shapes
C. different layer thickness
D. transistors
Answer: B
In Caltech intermediate form code, the design is given using geometric shapes. Boxes, polygons, and wires are readily defined.
86. The CIF dimensions are given in the form of
A. X, Y coordinates
B. lambda form
C. millimeter form
D. alpha form
Answer: A
The CIF dimensions and positions are given in X, Y coordinate form but are in absolute dimension units and not in lambda form.
87. Polygons in CIF are specified in terms of
A. length
B. width
C. vertices
D. angles
Answer: C
In CIF, polygons(P) are specified in terms of vertices in order. An n-sided polygon needs n vertices and a connection between first and last.
88. Wires are specified in terms of
A. vertices
B. width
C. angles
D. lengths
Answer: B
Wires(W) are specified in terms of their width followed by the center line’s coordinates of the wire’s path.
89. CIF can also accommodate rotations and translations.
A. true
B. false
Answer: A
CIF also accommodates cells and rotations and translations etc along with geometrically shaped designs.
90. If the vector coordinate is (1,0) it indicates that
A. length is parallel to the y-axis
B. length is parallel to the x-axis
C. width is parallel to the y-axis
D. width is parallel to the x-axis
Answer: B
If the vector coordinate is (1,0), it denotes that the length will be parallel to the x-axis. The direction is always assumed parallel to the length.
91. In which layer do the geometrical structures exist?
A. metal
B. silicon
C. silicide
D. diffusion
Answer: B
In CIF design is done using geometrical structures like boxes, polygons, etc and these boxes exist in the silicon layer.
92. Physical verification tools in the design process include
A. circuit extractors
B. textual entry
C. graphical entry
D. simulation
Answer: A
Physical verification tools in the design process include design rule checking, circuit extractors, ratio rule, and other static checks.
93. Behavioral tools contain
A. graphical entry
B. design check
C. performance check
D. simulation
Answer: D
Behavioral tools contain simulation at various levels. It will be required to check out the design before turning out the design into silicon.
94. Simulators are available for
A. transistor-level logic
B. switch level logic
C. gate-level logic
D. design level logic
Answer: B
Simulators are available for switch-level logic and timing simulation. This is used to check out the design.
95. Selection and placement is done using
A. cursor
B. shapes
C. textual
D. graphical
Answer: A
Selection and placement of geometric shapes are done using some form of the cursor and it may also allow the selection of menu items.
96. Cursor position is controlled using
A. mouse
B. bit pad digitizer
C. mouse and bit pad digitizer
D. keyboard
Answer: C
The positioning of the cursor may be affected by the keyboard and the cursor position is controlled by a bit pad digitizer or a mouse.
97. CIF code is a ______ layout language.
A. mask level
B. floor level
C. design level
D. transistor level
Answer: A
CIF is an example of mask-level layout language, which is well suited to physical layout description but not for capturing the design intent.
98. Which verification capture’s design intent and not the physical layout?
A. mask level layout language
B. transistor level layout language
C. circuit description language
D. switch level layout language
Answer: C
Circuit description language where the primitives are circuit elements such as transistors, wires, and nodes. It captures the design intent and not directly the physical layout.
99. All possible errors in mask layout can be eliminated after mask-making proceeds.
A. true
B. false
Answer: B
The cost in time and the facilities in mask-making is such that all the possible errors must be eliminated before mask-making proceeds.
100. The nature of physical layout verification software depends on
A. absolute design rules
B. fixed layout
C. virtual grid layout
D. all of the mentioned
Answer: D
The nature of physical layout verification design rule checking software depends on whether the design rules are absolute or lambda-based or on whether or not the layout is on a fixed or virtual grid.
