101. Which is used to interpret physical layout in circuit terms?
A. circuit converter
B. layout converter
C. circuit extractor
D. layout extractor
Answer: C
A circuit extractor is used to convert the design information which is in the form of physical layout data to circuit terms.
102. _______ is the solution of appropriate process material and energy balances.
A. Flow sheeting
B. Flow processing
C. Flow Solving
D. None of the mentioned
Answer: a
Flow sheeting is the solution of appropriate process material and energy balances.
103. Process simulator is the computer code used in _______
A. Flow sheeting
B. Flow processing
C. Flow Solving
D. None of the mentioned
Answer: a
Process simulator is the computer code used in flow sheeting.
104. Calculation of _____________ is the fundamental of flow sheeting codes.
A. Mass balance
B. Mole balance
C. Energy balance
D. None of the mentioned
Answer: a
Calculation of mass balance is fundamental to flow sheeting codes.
105. Which of the following is a feature of the process simulator?
A. Equipment sizing functions
B. Import and export data
C. Scheduling of batch operations
D. All of the mentioned
Answer: d
The feature of the process simulator is
Equipment sizing functions
Import and export data
Scheduling of batch operations
106. What is the product enthalpy of 1 mole of the product? The feed of a process simulator is 1 mole with enthalpy 2 J/mole, the heat input is 4 J, and the work performed is 5 J.
A. 1 J/mole
B. 2 J/mole
C. 3 J/mole
D. 5 J/mole
Answer: c
Energy balance, H = 2 + 4 – 5 = 1 J/mole.
107. What is the product enthalpy of a process simulator if the feed is 15 J, the heat input is 10 J, and the work performed is 5 J?
A. 10 J
B. 15 J
C. 20 J
D. 25 J
Answer: c
Energy balance, H = 15 + 10 – 5 = 20 J.
108. The interconnection equations are for a _______ model.
A. Mixing
B. Splitting
C. Process
D. All of the mentioned
Answer: a
The mixing model is for interconnection equations.
109. While solving a process simulation, the required balance is?
A. Material balances
B. Equilibrium relations
C. Energy balances
D. All of the mentioned
Answer: d
All three are required for solving the process simulator.
110. The input mass in a process simulator is X Kg and the output mass is Y Kg. Then
A. X = Y
B. X > Y
C. X < Y
D. None of the mentioned
Answer: a
The input mass in a process simulator is X Kg and the output mass is Y Kg. Then the mass balance, product mass = feed mass i.e X = Y.
111. The input mass in a process simulator is 2 Kg and the output mass is ______ Kg.
A. 1
B. 2
C. 3
D. 4
Answer: b
Since Mass balance, product mass = feed mass.
The input mass in a process simulator is 2 Kg and the output mass is 2 kG.
112. Simulator converts circuit information to
A. design plan
B. does verification
C. set of equations
D. floor plan
Answer: C
The circuit description contains information about circuit components and interconnections. This is transformed using a simulator into a set of equations from which predictions of behavior are made.
113. The electrical behaviour of a circuit is given using
A. design rules
B. floor plan
C. structures and layouts
D. mathematical modelling
Answer: D
The electrical behavior is defined by mathematical modeling and its accuracy is measured using the accuracy of simulation and computing power and time for simulation.
114. Which gives the main electrical behaviour of various parts of the circuit?
A. circuit simulator
B. timing simulator
C. logic level simulator
D. functional simulator
Answer: A
Circuit simulators are concerned with the electrical behaviour of the various parts of the circuit to be implemented in silico
n.
115. Which takes lots of simulating time?
A. circuit simulator
B. timing simulator
C. logic level simulator
D. functional simulator
Answer: A
Circuit simulators take a lot of computing time to simulate even a small section of the system and are completely impractical for circuits of any real magnitude.
116. Timing simulator concentrates on
A. quiescent nodes
B. active nodes
C. passive nodes
D. electrical nodes
Answer: B
The timing simulator concentrates on active nodes and ignores the quiescent nodes in simulation and improves the design accordingly.
117. The accuracy of the simulation depends on the accuracy of
A. fabrication house parameters
B. electrical parameters
C. active parameters
D. functional parameters
Answer: A
The accuracy of the simulation depends on the accuracy of fabrication house parameters which must be fed into the simulator which is in the range of 20% or better.
118. Which is important during the design phase?
A. circuit simulator
B. timing simulator
C. logic level simulator
D. functional simulator
Answer: B
Timing simulators are increasingly important during the design phase because of their speed and consequent interactive qualities.
119. Run times are _______ to a number of devices and nodes.
A. linearly related
B. inversely related
C. exponentially equal
D. does not relate
Answer: A
Run time is linearly related to the number of devices and nodes being simulated. The structure of timing simulator tools ensures this relationship.
120. Improvement of transistor modelling includes
A. body effect
B. channel length modulation
C. carrier velocity saturation
D. all of the mentioned
Answer: D
To improve the transistor modeling it is possible to include body effect, channel length modulation and carrier velocity saturation.
121. Channel length modulation is for voltages
A. exceeding threshold
B. exceeding onset of saturation
C. exceeding power supply
D. exceeding onset of non-saturation
Answer: B
Channel length modulation is for voltages exceeding the onset of saturation there is an effective decrease in channel length of a short channel transistor.
122. The charge carriers reach _________ scattering limited velocity before pinch-off.
A. maximum
B. minimum
C. less
D. equal
Answer: A
Velocity saturation occurs when the drain to source voltage of a short channel transistor exceeds a critical value, and the charge reaches its maximum scattering limited velocity before pinch-off.
123. Less current is available from
A. short channel transistor
B. large channel transistor
C. very large channel transistor
D. does not depend on channel transistor
Answer: A
Less current is available from a short channel transistor than from a long channel transistor with similar width to length ratio and processing.
124. Which can cope with large sections of layout?
A. circuit simulator
B. timing simulator
C. logic level simulator
D. functional simulator
Answer: C
The logic level simulator can cope with a large section of the layout at one time but the performance is assumed in terms of logic levels with no or little timing information.
125. Logic simulators can be replaced by simulators that operate at the transistor level.
A. true
B. false
Answer: B
Logic simulators may be replaced by simulators which operate at the register transfer level.
126. Circuit nodes cannot be probed for monitoring or excitation.
A. true
B. false
Answer: A
The entire surface of the chip other than the pads are sealed by cover glass layers and thus circuit nodes cannot be probed for monitoring and excitation.
127. The circuit should be tested at
A. design level
B. chip level
C. transistor level
D. switch level
Answer: B
Chip design mistakes can be very costly both in terms of time and money. The circuit should be tested at chip level itself. Design for testability is essential for good design.
128. ______ of the area is dedicated for testability.
A. 20%
B. 10%
C. 30%
D. 25%
Answer: C
Design for testability is an essential process for good design. Thus the designers dedicate around 30% or more of the chip area for testing.
129. Partitioning into subsystems is done at
A. design stage
B. prototype stage
C. testing stage
D. fabrication stage
Answer: B
At the prototype stage, partitioning into subsystems are done to solve all the complex problem. Each of these subsystems is self-contained and independent.
130. In prototype testing, the circuits are
A. open circuited
B. short-circuited
C. tested as a whole circuit
D. programmed
Answer: A
The connections are made open-circuited so that one system can be divorced from another as a last resort in prototype testing.
132. The number of test vectors for exhaustive testing is calculated by
A. 2(m+n)
B. 2((m+n)/2)
C. 2(m-n)
D. 22(m+n)
Answer: A
The total number of test vectors for exhaustive testing is given by 2(m+n). For example, if m is 20 and n is 24, the resultant number of test vectors for exhaustive testing is 244.
133. After partitioning, the number of vectors is given by
A. 2(m+n)
B. 2((m+n)/2)
C. 2n+ 2m
D. 22(m+n)
Answer: C
If the system is partitioned for testing, exhaustive testing can be reduced to 2n + 2m a much more reasonable proportion.
134. What are the dominant faults in diffusion layers?
A. short circuit faults
B. open circuit faults
C. short and open circuit faults
D. power supply faults
Answer: A
In MOS circuits, short circuits and open circuits in the metal layer and short circuits in the diffusion layer are the dominant faults experienced.
135. Test pattern generation is assisted using
A. automatic test pattern generator
B. exhaustive pattern generator
C. repeated pattern generator
D. loop pattern generator
Answer: A
Test pattern generation is assisted using automatic test pattern generators but they are complicated to use properly and ATPG costs tend to rise rapidly with circuit size.
136. _____ of faults are easier to detect.
A. 50%
B. 60%
C. 70%
D. 80%
Answer: D
It is relatively easy to detect the first 80% of faults using various classical test strategies.
137. Hot carrier injection causes
A. threshold voltage shift
B. transconductance degradation
C. threshold voltage shift & transconductance degradation
D. none of the mentioned
Answer: C
Hot carrier injection causes both threshold voltage shift and transconductance degradation due to charge accumulation in the gate oxide.
138. Oxide breakdown occurs due to
A. electrostatic charge
B. threshold voltage
C. voltage shift
D. poor input/output pad circuitry
Answer: D
Oxide breakdown occurs due to inadequate protection against electrostatic discharge and also due to defects or poor design in input/output pad circuitry.
139. Which model is used for pc board testing?
A. stuck at
B. stuck in
C. stuck on
D. stuck through
Answer: A
The stuck-at model is used in the testing of pc boards and is not sufficient to test actual VLSI CMOS circuits.
140. The input signal combination in exhaustive testing is given as
A. 2N
B. 21/N
C. 2(M+N)
D. 1/2N
Answer: A
For testing an N input circuit using exhaustive testing, the total number of input combinations can be given as 2N.
141. Observability is the process of
A. checking all inputs
B. checking all outputs
C. checking all possible inputs
D. checking errors and performance
Answer: B
Observability is the process of observing outputs for all the input combinations.
142. Exhaustive testing is suitable when N is
A. small
B. large
C. any value for N
D. very large
Answer: A
Exhaustive testing is the process where all possible input combinations are used. This is suitable when N is relatively small.
143. Test vectors in sensitized path-based testing is generated
A. before enumerating faults
B. after enumerating faults
C. after designing
D. before designing
Answer: B
In sensitized path-based testing, test vectors are generated after enumerating the possible faults because many patterns may not occur during the application of the circuit.
144. To propagate the fault along the selected path to primary output, setting _____ is done.
A. AND to 1
B. OR to 1
C. NOR to 1
D. NAND to 0
Answer: A
Inputs of another gate are determined so as to propagate the fault signal along the selected path to the primary output of the circuit. This is done by setting AND/NAND to 1 and OR/NOR to 0.
145. In consistency/ justification, tracking is done
A. forward from gate input to primary input
B. backward from the gate input to the primary output
C. backward from the gate input to primary input
D. forward from gate output to the primary output
Answer: C
The consistency step finds the input patterns to realize all the necessary values. This is done by tracking backward from gate input to the primary input of the logic.
146. In D-algorithm, a particular ______ fault is detected by examining the _____ conditions.
A. internal, output
B. internal, input
C. external, output
D. external, input
Answer: A
In a circuit comprising combinational logic, D-algorithm aims at detecting a particular internal fault by examining the output conditions.
147. D-algorithm is based on
A. existence of one fault machine
B. existence of one good machine
C. existence of one fault and one good machine
D. existence of two fault machines alone
Answer: C
D-algorithm is based on the hypothesis of the existence of two machines – one good machine and one faulty machine.
148. The existence of a fault in the faulty machine causes a discrepancy in the behavior of the circuit for all values on inputs.
A. true
B. false
Answer: B
The existence of a fault in a faulty machine causes a discrepancy in its behavior and that of the good machine for some particular values of inputs.
149. In D-algorithm, the discrepancy is driven to _____ and observed and thus detected.
A. all inputs
B. particular inputs
C. output
D. end of the circuit
Answer: C
In D-algorithm, a systematic means is provided to drive the discrepancy to output and it is observed and detected.
150. D-algorithm is time-intensive for large circuits.
A. true
B. false
Answer: A
D-algorithm is extremely time-intensive and computing-intensive for large circuits and many modifications and improvements are done.
