SPARC and MIPS processors are the first generation processors of RISC architecture.
2. What is the 80/20 rule?
A. 80% instruction is generated and 20% instruction is executed
B. 80% instruction is executed and 20% instruction is generated
C. 80%instruction is executed and 20% of instruction is not executed
D. 80% of instruction is generated and 20% of instructions are not generated
Answer: A
80% of instructions are generated and only 20% of the instruction set is executed that is, by simplifying the instructions, the performance of the processor can be increased which leads to the formation of RISC which is a reduced instruction set computing.
3. Which of the architecture is more complex?
A. SPARC
B. MC68030
C. MC68030
D. 8086
Answer: A
SPARC has RISC architecture which has a simple instruction set but MC68020, MC68030, and 8086 have CISC architecture which is more complex than CISC.
4. Which is the first company that defined RISC architecture?
A. Intel
B. IBM
C. Motorola
D. MIPS
Answer: B
In the 1970s IBM identified RISC architecture.
5. Which of the following processors execute its instruction in a single cycle?
A. 8086
B. 8088
C. 8087
D. MIPS R2000
Answer: D
MIPS R2000 possesses RISC architecture in which the processor executes its instruction in a single clock cycle and also synthesizes complex operations from the same reduced instruction set.
6. How is memory accessed in RISC architecture?
A. load and store instruction
B. opcode instruction
C. memory instruction
D. bus instruction
Answer: A
The data of the memory address is loaded into a register and manipulated, its contents are written out to the main memory.
7. Which of the following has Harvard architecture?
A. EDSAC
B. SSEM
C. PIC
D. CSIRAC
Answer: C
PIC follows Harvard architecture in which the external bus architecture consists of separate buses for instruction and data whereas SSEM, EDSAC, and CSIRAC are stored-program architecture.
8. Which of the following statements are true for von Neumann architecture?
A. shared bus between the program memory and data memory
B. separate bus between the program memory and data memory
C. external bus for program memory and data memory
D. external bus for data memory only
Answer: A
von Neumann architecture shares a bus between program memory and data memory whereas Harvard architecture has a separate bus for program memory and data memory.
9. What is CAM stands for?
A. content-addressable memory
B. complex addressable memory
C. computing addressable memory
D. concurrently addressable memory
Answer: A
Non-von Neumann architecture is based on content-addressable memory.
10. Which of the following processors uses Harvard architecture?
A. TEXAS TMS320
B. 80386
C. 80286
D. 8086
Answer: A
It is a digital signal processor which has small and highly optimized audio or video processing signals. It possesses multiple parallel data buses.
