Sample and Hold Circuits MCQ Quiz – Objective Question with Answer for Sample and Hold Circuits

1. What is the ideal reconstruction formula or ideal interpolation formula for x(t) = _________

a) $$\sum_{-\infty}^\infty x(nT) \frac{sin⁡(π/T) (t-nT)}{(π/T)(t-nT)}$$

b) $$\sum_{-\infty}^\infty x(nT) \frac{sin⁡(π/T) (t+nT)}{π/T)(t+nT}$$

c) $$\sum_{-\infty}^\infty x(nT) \frac{sin⁡(2π/T) (t-nT)}{2π/T)(t-nT}$$

d) $$\sum_{-\infty}^\infty x(nT) \frac{sin⁡(4π/T) (t-nT)}{(4π/T)(t-nT)}$$

x(t) = $$\sum_{-\infty}^\infty x(nT) \frac{sin⁡(π/T) (t-nT)}{(π/T)(t-nT)}$$ where the sampling interval T = 1/Fs=1/2B, Fs is the sampling frequency and B is the bandwidth of the analog signal.

2. What is the new ideal interpolation formula described after few problems with previous one?

a) g(t)=$$\frac{sin⁡(2πt/T)}{(πt/T)}$$

b) g(t)=$$\frac{sin⁡(πt/T)}{(πt/T)}$$

c) g(t)=$$\frac{sin⁡(6 πt/T)}{(πt/T)}$$

d) g(t)=$$\frac{sin⁡(3 πt/T)}{(πt/T)}$$

The reconstruction of the signal x (t) from its samples as an interpolation problem and have described the function:g(t)=$$\frac{sin⁡(πt/T)}{(πt/T)}$$.

3. What is the frequency response of the analog filter corresponding to the ideal interpolator?

a) H(F)=$$\begin{cases}T, |F|≤ \frac{1}{2T} = F_s/2\\0,|F| > \frac{1}{4T}\end{cases}$$

b) H(F)=$$\begin{cases}T, |F|≥ \frac{1}{2T} = F_s/2\\0,|F| > \frac{1}{4T}\end{cases}$$

c) H(F)=$$\begin{cases}T, |F|≤ \frac{1}{2T} = F_s/2\\0,|F| > \frac{1}{2T}\end{cases}$$

d) H(F)=$$\begin{cases}T, |F|≤ \frac{1}{4T} = F_s/2\\0,|F| > \frac{1}{4T}\end{cases}$$

The analog filter corresponding to the ideal interpolator has a frequency response:
H(F)=$$\begin{cases}T, |F|≤ \frac{1}{2T} = F_s/2\\0,|F| > \frac{1}{2T}\end{cases}$$, H(F) is the Fourier transform of the interpolation function g(t).

4. The reconstruction of the signal from its samples as a linear filtering process in which a discrete-time sequence of short pulses (ideally impulses) with amplitudes equal to the signal samples, excites an analog filter.

a) True
b) False

The reconstruction of the signal from its samples as a linear filtering process in which a discrete-time sequence of short pulses (ideally impulses) with amplitudes equal to the signal samples, excites an analog filter.

5. The ideal reconstruction filter is an ideal low pass filter and its impulse response extends for all time.
a) True
b) False

The ideal reconstruction filter is an ideal low pass filter and its impulse response extends for all time. Hence the filter is noncausal and physically non realizable. Although the interpolation filter with impulse response given can be approximated closely with some delay, the resulting function is still impractical for most applications where D/A conversion is required.

6. D/A conversion is usually performed by combining a D/A converter with a sample-and-hold (S/H ) and followed by a low pass (smoothing) filter.

a) True
b) False

D/A conversion is usually performed by combining a D/A converter with a sample-and-hold (S/H) and followed by a low pass (smoothing) filter. The D/A converter accepts at its input, electrical signals that correspond to a binary word, and produces an output voltage or current that is proportional to the value of the binary word.

7. The time required for the output of the D/A converter to reach and remain within a given fraction of the final value, after application of the input codeword is called?

a) Converting time
b) Setting time
c) Both Converting & Setting time
d) None of the mentioned

An important parameter of a D/A converter is its settling time, which is defined as the time required for the output of the D/A converter to reach and remain within a given fraction (usually,±1/2 LSB) of the final value, after the application of the input codeword.

8. In the D/A converter, the application of the input codeword results in a high-amplitude transient, called?

a) Glitch
b) Deglitch
c) Glitter
d) None of the mentioned

The application of the input codeword results in a high-amplitude transient, called a “glitch”. This is especially the case when two consecutive code words to the A/D differ by several bits.

9. In a D/A converter, the usual way to solve the glitch is to use deglitcher. How is the Deglitcher designed?

a) By using a low pass filter
b) By using a S/H circuit
c) By using a low pass filter & S/H circuit
d) None of the mentioned

The usual way to remedy this problem is to use an S/H circuit designed to serve as a “deglitcher”. Hence the basic task of the S/H is to hold the output of the D/A converter constant at the previous output value until the new sample at the output of the D/A reaches a steady state, and then it samples and holds the new value in the next sampling interval. Thus the S/H approximates the analog signal by a series of rectangular pulses whose height is equal to the corresponding value of the signal pulse.

10. What is the impulse response of an S/H, when viewed as a linear filter?

a) h(t)=$$\begin{cases}1,0≤t≤T\\0,otherwise\end{cases}$$

b) h(t)=$$\begin{cases}1,0≥t≥T\\0,otherwise\end{cases}$$

c) h(t)=$$\begin{cases}1,0<t≤T\\0,otherwise\end{cases}$$

d) None of the mentioned

When viewed as a linear filter, the S/H has an impulse response:

h(t)=$$\begin{cases}1,0≤t≤T\\0,otherwise\end{cases}$$

11. A good Sample and Hold circuit should have

1. High input impedance
2. Low output impedance
3. Both 1 and 2
4. None of the above

Answer. 3. Both 1 and 2

Sample and Hold (S/H) circuit:

It is used with an analog to digital converter to sample the input analog signal and hold the sample signal.

A Sample and Hold Circuit should have high input impedance and low output impedance because due to the high input impedance loading effect. It is the degree to which a measurement instrument impact electrical properties (Voltage, Current, resistance) of a Circuit] is less and Circuit performance is better

For better circuit performance input impedance should be high and output impedance should be low.

12. Sample-and-hold circuits in ADCs are designed to

1. sample and hold the output of the binary counter during the conversion process
2. stabilize the ADCs threshold voltage during the conversion process
3. stabilize the input analog signal during the conversion process
4. sample and hold the ADC staircase waveform during the conversion process

Answer. 3. stabilize the input analog signal during the conversion process

• Sample & Hold Circuit is used to sample the given input signal and to hold the sampled value.
• Out of different ADCs, successive approximation type ADC uses an S/H circuit, where the signal is to be held constant while A to D conversion is taking place.
• They are also used in DACs for the same purpose.
• It is used in analog demultiplexing in data distribution and in analog delay lines.
• In general, S/H circuits are used in all applications where it is necessary to stabilize the analog signal for further processing.

13. When a time-varying signal has to be digitized using an ADC, which of the following is necessary to use before digitization?

1. Time-division multiplexer
2. Frequency division multiplexer
3. Sample and hold circuit
4. Instrument amplifier

Answer. 3. Sample and hold circuit

When a time-varying signal has to be digitized using an ADC, a sample and hold circuit is necessary to use before digitation. Because sample and hold circuit take sample at a particular instant.

14. For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then

1. droop rate decreases and acquisition time decreases
2. droop rate decreases and acquisition time increases
3. droop rate increases and acquisition time decreases
4. droop rate increases and acquisition time increases

Answer.2. droop rate decreases and acquisition time increases

For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then the droop rate decreases and acquisition time increases.

$${I_{max}} = {C_H} \times \left( {\frac{{d{V_o}}}{{dt}}} \right)$$

$${I_{max}} = \;{C_H} \times \left( {\frac{{d{V_o}}}{{dt}}} \right) = Constant\ If C­H increases then ‘t’ which is the acquiring time must also increase to maintain the relationship. Also, capacitor discharging time constant TC(discharge) is proportional to capacitance i.e. \({T_{{C_{discharge}}}} \propto {C_H}$$

So if CH increases then capacitor voltage decreases slowly because of discharging time constant, this means droop rate decreases.

15. Increase the order of data hold will

1. improve the stability of the system
2. decrease the time delay
3. increase the time delay
4. increase the time constant

Data hold is a process of generating a continuous-time signal h(t) from a discrete-time sequence x(kT).

The signal h(t) during the time interval kT ≤ t ≤ (k + 1)T may be approximated by a polynomial in τ as follows:

As the order of the data hold increases the circuit order(n) also increases which leads to a further increase in the time delay because it has to use past n + 1 samples.

16. A signal channel signal acquisition system with 0-10 V range consists of a sample and hold circuit with a worst-case drop rate of 100 μV/ms and 10 bit ADC. The maximum conversion time for the ADC is

1. 49 ms
2. 0.49 ms
3. 4.9 ms
4. 490 ms

In an ADC along with sample and hold circuit, for avoiding error at the output, the voltage of the capacitor should be not dropped by more than ± Δ/2

$${\rm{\Delta }} = \frac{{10}}{{{2^{10}} – 1}} = 9.77 \times {10^{ – 3}}V$$

Δ/2 = 4.88 × 103 V

Maximum conversation time for the ADC is

$$t = \frac{{\frac{{{\rm{\Delta }}}}{2}}}{{drop\;rate}} = \frac{{4.88 \times {{10}^{ – 3}}V}}{{100 \times {{10}^{ – 4}}V/msec}}$$

= 48.87 msec ≈ 49 msec

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