11. Which of the following are accessible by the ISR in the software interrupt mechanism?
A. register
B. interrupt
C. nmi
D. memory
Answer: A
The additional data are offered by certain registers and these additional data are used to specify the type of the data parameter and the request with the specific ISR when running in the software interrupt mode.
12. What allows the data protection in the software interrupt mechanism?
A. Different mode
B. Same mode
C. SWI
D. TRAP
Answer: A
The switching between user mode and supervisor mode provides protection for the processor, that is, the different modes in the software interrupt allow the memory and the associated code and data to be protected from each other.
13. What does NMI stand for?
A. non-machine interrupt
B. non-maskable interrupt
C. non-massive interrupt
D. non-memory interrupt
Answer: B
The NMI stands for the non-maskable interrupt in which the external interrupts cannot be masked out.
14. Which NMI is used in the IBM PC?
A. SWI
B. TRAP
C. 80×86 NMI
D. Maskable interrupt
Answer: C
The most commonly used non-maskable interrupt is the 80×86 NMI, which is implemented in the IBM PC.
15. Which can be used to pass the status information to the calling software in the software interrupt mechanism?
A. register
B. memory
C. flag
D. nmi
Answer: A
In order to use the software interrupt more effectively, the additional data are used to specify the type of the request, and data parameters are passed to the specific ISR. This additional data are offered by certain registers. These registers are accessible by the ISR and they can also be used to pass the status information back to the calling software.
16. Which of the following uses clock edge to generate an interrupt?
A. edge-triggered
B. level-triggered
C. software interrupt
D. nmi
Answer: A
In the edge-triggered interrupt, the clock edge is used to generate an interrupt. The transition is from a logical low to high or vice versa.
17. In which interrupt, the trigger is dependent on the logic level?
A. edge-triggered
B. level-triggered
C. software interrupt
D. nmi
Answer: B
In the level-triggered interrupt, the trigger is completely dependent on the logic level. The processors may require the level to be in a certain clock width so that the shorter pulses which are shorter than the minimum pulse width are ignored.
18. At which point the processor will start to internally process the interrupt?
A. interrupt pointer
B. instruction pointer
C. instruction boundary
D. interrupt boundary
Answer: C
After the recognition of the interrupt, and finds that it is not an error condition with the currently executing interrupt, then the interrupt will not be internally executed until the current execution has been completed. This point is known as the instruction boundary. At this point, the processor will start to internally process the interrupt.
19. What does 80×86 use to hold essential data?
A. stack frame
B. register
C. internal register
D. flag register
Answer: A
The MC68000 and 80×86 families use stack frames for holding the data whereas RISC processors use special internal registers.
20. What does the RISC processor use to hold the data?
A. flag register
B. accumulator
C. internal register
D. stack register
Answer: C
The RISC processors use special internal registers to hold data whereas the 80×86 and MC68000 family uses stack register to hold the data.
