21. Which of the following is a stack-based processor?
A. MC68000
B. PowerPC
C. ARM
D. DEC Alpha
Answer: A
The MC68000, Intel 80×86, and most of the b-bit controllers are based on stack-based processors whereas PowerPC, DEC Alpha, and ARM are RISC families which have a special internal register for holding the data.
22. Which of the following is used to reduce the external memory cycle?
A. internal hardware stack
B. internal software stack
C. external software stack
D. internal register
Answer: A
Some of the processors use an internal hardware stack which helps in reducing the external memory cycle necessary to store the stack frame.
23. How many interrupt levels are supported in the MC68000?
A. 2
B. 3
C. 4
D. 7
Answer: D
The MC68000 has an external stack for holding the data. The MC68000 family supports seven interrupt levels which are encoded into three interrupt pins.
24. How many interrupt pins are used in MC68000?
A. 2
B. 3
C. 4
D. 5
Answer: B
The MC68000 family supports seven interrupt levels which are encoded into three interrupt pins. These interrupt pins are IP0, IP1, and IP2.
25. Which priority encoder is used in MC68000?
A. 4-to-2 priority encoder
B. LS148 7-to-3
C. 2-to-4 priority encoder
D. LS148 3-to-7
Answer: B
The LS148 7-to-3 priority encoder is used in MC68000. This converts the seven external pins into a three-bit binary code.
26. Which of the following converts the seven external pins into a 3-bit binary code?
A. priority encoder
B. 4-to-2 priority encoder
C. LS148 7-to-3
D. 2-to-4 priority encoder
Answer: C
The LS148 7-to-3 priority encoder can convert the seven external pins into a three-bit binary code.
27. Which of the following ensures the recognition of the interrupt?
A. interrupt ready
B. interrupt acknowledge
C. interrupt terminal
D. interrupt start
Answer: B
The interrupt level remains asserted until its interrupt acknowledgment cycle ensures the recognition of the interrupt.
28. Which of the following is raised to the interrupt level to prevent the multiple interrupt request?
A. internal interrupt mask
B. external interrupt mask
C. non-maskable interrupt
D. software interrupt
Answer: A
The internal interrupt mask is raised to the interrupt level, to prevent the multiple interrupt acknowledgments.
29. What does MSR stand for?
A. machine state register
B. machine software register
C. minimum state register
D. maximum state register
Answer: A
The MSR is a machine state register. When the exception is recognized, the address of the instruction and the MSR is stored in the supervisor registers while handling an exception.
30. How many supervisor registers are associated with the exception mode?
A. 2
B. 3
C. 4
D. 5
Answer: A
When the exception is recognized, the address of the instruction and the machine state register(MSR) are stored in the supervisor registers in the exception mode. There are two supervisor registers SRR0 and SRR1.
