21. In Pseudo-nMOS logic, n transistor operates in
A. cut off region
B. saturation region
C. resistive region
D. non-saturation region
Answer: B
In Pseudo-nMOS logic, n transistor operates in a saturation region and the p transistor operates in a resistive region.
22. The power dissipation in Pseudo-nMOS is reduced to about ________ compared to nMOS device.
A. 50%
B. 30%
C. 60%
D. 70%
Answer: C
The power dissipation in Pseudo-nMOS is reduced to about 60% compared to nMOS devices.
23. Pseudo-nMOS has higher pull-up resistance than nMOS devices.
A. true
B. false
Answer: A
Pseudo-nMOS has higher pull-up resistance than nMOS devices and thus inverter pair delay is larger.
24. In dynamic CMOS logic _____ is used.
A. two-phase clock
B. three-phase clock
C. one phase clock
D. four-phase clock
Answer: D
In dynamic CMOS logic, a four-phase clock is used in which actual signals are used to derive the clocks.
25. In clocked CMOS logic, output in evaluated in
A. on period
B. off period
C. both periods
D. half of on period
Answer: A
In clocked CMOS logic, the logic is evaluated only in the on the period of the clock. And owing to the extra transistor in series, slower rise time and fall times are expected.
26. In clocked CMOS logic, rise time and fall time are
A. faster
B. slower
C. faster first and then slows down
D. slower first and then speeds up
Answer: B
In clocked CMOS logic, rise time and fall time are slower because of more number of transistors in series.
27. In CMOS domino logic _____ is used.
A. two-phase clock
B. three-phase clock
C. one phase clock
D. four-phase clock
Answer: C
In CMOS domino logic, a single-phase clock is used. Clock signals distributed on one wire are called a single or one-phase clock.
28. CMOS domino logic is the same as ______ with an inverter at the output line.
A. clocked CMOS logic
B. dynamic CMOS logic
C. gate logic
D. switch logic
Answer: B
CMOS domino logic is the same as that of the dynamic CMOS logic with an inverter at the output line.
29. CMOS domino logic occupies
A. smaller area
B. larger area
C. smaller & larger area
D. none of the mentioned
Answer: A
CMOS domino logic structure occupies a smaller area than conventional CMOS logic as only n-block is used.
30. CMOS domino logic has
A. smaller parasitic capacitance
B. larger parasitic capacitance
C. low operating speed
D. very large parasitic capacitance
Answer: A
CMOS domino logic has smaller parasitic capacitance and higher operating speed.
