1. Which provides large capacitance?
A. load capacitance
B. bus wiring capacitance
C. sheet capacitance
D. area capacitance
Bus wiring capacitance Cbus provides the largest capacitance for a typical bus system for example for small chips this can be as high as 0.8pF.
2. Bus wiring capacitance is driven through
A. one transistor
B. two transistors
C. three transistors
D. no transistors
Bus wiring capacitance is driven through pull-up and pull-down transistors and through at least one pass transistor or transmission gate in the series.
3. What is the delay of input pads?
The input pad always contains overvoltage protection circuitry and Schmitt trigger circuitry. Its total delay is 30Ʈ.
4. The total delay for the select register circuit is
The total delay for the select register is 73Ʈ. It is the sum of delays of the input pad, three pass transistors, and driver inverter pair.
5. Delay for data propagation is
A. 10 nsec
B. 50 nsec
C. 100 nsec
D. 150 nsec
Data is propagated through the bus. The bus can be bidirectional but data can be propagated through the bus only in one direction at a time. The delay for this data propagation is 100 nsec.
6. Which is the longest delay in the adder process?
A. sum delay
B. carry delay
C. propagation delay
D. inverter delay
The longest delay in the adder process is the carry chain delay. This is the process of forming carry out which propagates through all bits of the adder.
7. The total delay for the adder process is
A. 100 nsec
B. 200 nsec
C. 220 nsec
D. 250 nsec
The total delay for the adder process is 220 nsec. The total delay is the sum of select register delays, bus delays, and carries chain delays.
8. The refreshing clock period should propagate through
A. memory cell
C. carry chain
D. any subunit
Clock 2 which is the refreshing clock should propagate through wiring and finite rise and fall time must be allowed.
9. The value of Ʈ for 5-micron technology is always constant.
The range of value of Ʈ for 5-micron technology was calculated to be 0.1 to 0.3 nsec but it may vary upto 0.6 nsec.
10. The total clock period for the adder process is
A. 100 nsec
B. 150 nsec
C. 200 nsec
D. 250 nsec
The total clock period of the adder process is 250 nsec which is the sum of all the delays (220 nseC. and the period of different phases of the process.