11. The detectability profile can be determined using
A. D algorithm
B. Cellular automata
C. LFSR
D. Random testing
Answer: A
The detectability of every fault in the circuit fault is needed for better testing. To determine this detectability profile, the D algorithm is used which gives accurate results.
12. Automatic test pattern generator detects only the fault and not its cause.
A. true
B. false
Answer: B
The test patterns generated using an automatic test pattern generator are used to detect the faults and in some cases, it assists in finding the cause of the failure too.
13. The automatic test pattern generator method has ________ phases.
A. two
B. three
C. four
D. five
Answer: A
The automatic test pattern generator method has two phases – fault activation and fault propagation phase.
14. Faults that produce the same faulty behavior are known as
A. similar faults
B. equivalent faults
C. correlative faults
D. ambiguous faults
Answer: B
Two or more faults may produce the same faulty behavior for all input patterns and these faults are known as equivalent faults.
15. The process of removing equivalent faults is called as
A. equivalent removing
B. bulk damaging
C. fault collapsing
D. fault reduction
Answer: C
The process of removing equivalent faults from the entire set of faults is called as fault collapsing. Any single fault from the whole set of equivalent faults can represent it.
16. ‘n’ signal lines can potentially have _____ stuck-at faults.
A. n2
B. 2n
C. n
D. n/2
Answer: B
If a circuit has n signal lines, then potentially it can have 2n stuck-at faults defined on the circuit.
17. The stuck-at model is a _____ fault model.
A. recurring
B. equivalent
C. simple
D. logical
Answer: D
The stuck-at model is a logical fault model because no delay information is associated with the fault definition.
18. Stuck-at fault is an example of the ______ fault model.
A. transient
B. permanent
C. intermittent
D. simple
Answer: B
Stuck-at fault model is also called a permanent fault model because the faulty effect is assumed to be permanent.
19. Transient faults does not depend on operating condition.
A. true
B. false
Answer: B
Transient faults occur sporadically depending on operating conditions and on the data values on surrounding signal lines.
20. The _________ between two signals is called a bridging fault.
A. open circuit
B. break
C. connection
D. short circuit
Answer: D
A short circuit between two signal lines is called a bridging fault and it is similar to the stuck-at fault model.
21. The sum of all propagation delays along a single path is given as
A. gate delay fault
B. transition fault
C. path delay fault
D. propagation fault
Answer: C
Path delay fault is given as the sum of all propagation faults along a single path. This fault shows that delay of one or more paths exceeds the clock period.
22. Which method is more complex?
A. stuck at fault
B. CA
C. combinational ATPG
D. sequential ATPG
Answer: D
The sequential automatic test pattern generation method is more complex and remains a complex task for large highly sequential circuits.
23. Which are processing faults?
A. missing contact window
B. parasitic transistor
C. oxide breakdown
D. all of the mentioned
Answer: D
Some of the real defects in chips such as processing faults are missing contact windows, parasitic transistor,s and oxide breakdown.
24. Surface impurities occur due to ion migration.
A. true
B. false
Answer: A
Some of the material defects are bulk defects and surface impurities. Bulk defects are cracks and crystal imperfection and surface impurities occur due to ion migration.
25. Electromigration is a
A. processing fault
B. material defects
C. time-dependent failure
D. packaging fault
Answer: C
Different types of real defects in chips are processing faults, material defects, time-dependent failures, and packaging faults. Time-dependent failures are dielectric breakdown and electromigration.
26. Which relation is correct?
A. failure – error – fault
B. fault – error – failure
C. error – fault – failure
D. error – failure – fault
Answer: B
The relation fault – error – failure is correct. Error is caused by faults and failure which is a deviation of the circuit caused by error.
27. For a circuit with k lines __________ single stuck-at fault is possible.
A. k
B. 2k
C. k/2
D. k2
Answer: B
For a circuit with k lines, 2k single stuck-at faults are possible and 3k – 1 multiple stuck-at faults are possible.
28. Single stuck-at fault is technology independent.
A. true
B. false
Answer: A
The single stuck-at fault is technology independent. It can be applied to TTL, CMOS, etc. It is also design style independent.
29. For a n signal lines circuit _____________ bridging faults are possible.
A. n
B. 2n
C. n2
D. n/2
Answer: C
For circuits with n lines, n2 bridging faults are possible. The bridging fault occurs when two lines are connected when they should not be connected. It leads to wired AND or wired OR.
30. IDDQ fault occurs when there is
A. increased voltage
B. increased quiescent current
C. increased power supply
D. increased discharge
Answer: B
When the input is low, both P and N transistors are conducting causing an increase in quiescent current which leads to IDDQ fault.
