Transconductance and Voltage Swing in VLSI MCQ

11. For finding transconductance which is kept constant?

A. Vss
B. Vdd
C. Vds
D. Vgs

Answer: C

For finding transconductance, Vds is kept constant and the ratio of the variation or change in Ids and Vgs is obtained.

 

12. Transconductance value is the same in linear and saturation regions.

A. true
B. false

Answer: A

The transconductance value is the same in the case of linear and saturation regions whereas it is 0 in the cut-off region.

 

13. In a bipolar transistor, transconductance is _______ to collector current.

A. directly related
B. inversely related
C. exponentially related
D. not related

Answer: A

In a bipolar transistor, transconductance is directly proportional to the collector current. It is given as gm = Ic(q/kT).

 

14. Figure of merit does not depend on saturation velocity.

A. true
B. false

Answer: B

The figure of merit is directly related to saturation velocity Vsat. It can be given as ft = Vsat/2(pi*L).

 

15. Inverter uses D-MESFET as

A. load
B. switching device
C. controller
D. amplifier

Answer: A

Direct-coupled FET logic inverter uses both depletion and enhancement type devices. E-MESFET is used as a switching device and D-MESFET is used as a load.

 

16. The allowable output voltage is limited by

A. load resistance
B. load capacitance
C. barrier height
D. material used for barrier

Answer: C

The design of the inverter is similar to silicon nMOS circuitry and the allowable output voltage is limited by the barrier height of the Schottky gate diode.

 

17. For the depletion-mode transistor, the gate is connected to

A. Vdd
B. source
C. ground
D. drain

Answer: B

For the depletion-mode transistor, the gate is connected to the source and it is always on and only the characteristic curve Vgs=0 is suitable.

 

18. In DCFL inverter, enhancement mode device is called as

A. pull-down transistor
B. pull up transistor
C. buffer
D. combiner

Answer: A

In a direct-coupled FET logic inverter, the depletion mode device is called the pull-up, and the enhancement mode device is called as pull-down transistor.

 

19. Maximum voltage across enhancement mode device corresponds to the minimum voltage across depletion mode device.

A. true
B. false

Answer: A

In a direct-coupled FET logic inverter, maximum voltage across the enhancement mode device corresponds to the minimum voltage across the depletion-mode transistor.

 

20. When current begins to flow, output voltage

A. increases
B. decreases
C. remains constant
D. does not get affected

Answer: B

When Vin exceeds the threshold voltage, the current begins to flow. Then the output voltage Vout decreases and the transistor becomes resistive.

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