161. The output conductance value in cut off region is
A. Vds
B. 1
C. cannot be determined
D. 0
Answer: D
The output conductance value for the cut-off region is 0. This gives the slope of output characteristics.
162. To improve the switching speed
A. voltage swing should be increased
B. voltage swing should be decreased
C. gate length should be increased
D. gate thickness should be increased
Answer: A
To improve the switching speed, the logic voltage swing should be increased and the gate length should be reduced. The increase in switching speed results in an increase in dissipation.
163. The device is turns off when
A. Vlow > Vt
B. Vlow < Vt
C. Vhigh < Vt
D. Vhigh > Vt
Answer: B
To establish the logic voltage swing and to turn off the device, Vlow the low logic voltage level must be less than the threshold voltage Vt.
164. For finding transconductance which is kept constant?
A. Vss
B. Vdd
C. Vds
D. Vgs
Answer: C
For finding transconductance, Vds is kept constant and the ratio of the variation or change in Ids and Vgs is obtained.
165. The transconductance value is the same in linear and saturation regions.
A. true
B. false
Answer: A
The transconductance value is the same in the case of linear and saturation regions whereas it is 0 in the cut-off region.
166. In a bipolar transistor, transconductance is _______ to collector current.
A. directly related
B. inversely related
C. exponentially related
D. not related
Answer: A
In a bipolar transistor, transconductance is directly proportional to the collector current. It is given as gm = Ic(q/kT).
167. The figure of merit does not depend on saturation velocity.
A. true
B. false
Answer: B
The figure of merit is directly related to saturation velocity Vsat. It can be given as ft = Vsat/2(pi × L).
168. Inverter uses D-MESFET as
A. load
B. switching device
C. controller
D. amplifier
Answer: A
Direct-coupled FET logic inverter uses both depletion and enhancement type devices. E-MESFET is used as a switching device and D-MESFET is used as a load.
169. The allowable output voltage is limited by
A. load resistance
B. load capacitance
C. barrier height
D. material used for barrier
Answer: C
The design of the inverter is similar to silicon nMOS circuitry and the allowable output voltage is limited by the barrier height of the Schottky gate diode.
170. For the depletion-mode transistor, the gate is connected to
A. Vdd
B. source
C. ground
D. drain
Answer: B
For the depletion-mode transistor, the gate is connected to the source and it is always on and only the characteristic curve Vgs=0 is suitable.
171. In DCFL inverter, enhancement mode device is called as
A. pull-down transistor
B. pull up transistor
C. buffer
D. combiner
Answer: A
In a direct-coupled FET logic inverter, the depletion mode device is called the pull-up, and the enhancement mode device is called as pull-down transistor.
172. The maximum voltage across the enhancement mode device corresponds to the minimum voltage across the depletion mode device.
A. true
B. false
Answer: A
In a direct-coupled FET logic inverter, maximum voltage across the enhancement mode device corresponds to the minimum voltage across the depletion-mode transistor.
173. When current begins to flow, output voltage
A. increases
B. decreases
C. remains constant
D. does not get affected
Answer: B
When Vin exceeds the threshold voltage, the current begins to flow. Then the output voltage Vout decreases and the transistor becomes resistive.
174. The inverter threshold voltage is the point where
A. Vin = Vt
B. Vout = Vt
C. Vin = Vout
D. Vout is lesser than Vin
Answer: C
The point at which Vout = Vin, is denoted as Vinv. The transfer characteristic and Vinv can be shifted by variation of the ratio of pull-up to pull-down resistances.
175. For equal margin, Vinv is set as ______ of logic voltage swing.
A. equal
B. half of
C. one third
D. twice
Answer: B
Since the logic high level is limited by barrier potential then for equal margins Vinv is set to half of the logic voltage swing.
176. For E-MESFET, Vinv is set in midway between
A. Vdd and Vss
B. Vt and Vin
C. Vt and Vout
D. barrier potential and ground
Answer: D
In a pull-down device that is E-MESFET, the inverter threshold voltage Vinv is set midway between barrier potential and ground.
176. To improve packing density, the gate length should be smaller.
A. true
B. false
Answer: B
To improve packing density, the gate length should be larger for the pull-up device. This will reduce drain to source saturation current.
177. The ratio of Zp.u./Zp.d. for E-MESFET is
A. 1/10
B. 10/1
C. 4/1
D. 1/4
Answer: B
For E-MESFET, the Zp.u./Zp.d. ratio is 10/1.
For MESFET with Lp.u.=Lp.d.
Wp.u./Wp.d. is equal to 1/10.
178. In direct coupled logic, the input transistor base is connected to
A. base output
B. emitter output
C. collector output
D. ground
Answer: C
In directly coupled logic, the input transistor base is directly connected to the collector output without any base resistors.
179. Direct-coupled logic is easy to design.
A. true
B. false
Answer: A
Direct-coupled logic devices have fewer components, are economical, and are simpler to design and fabricate.
180. For cascade inverters, the relation suitable is
A. Vin = Vout > Vinv
B. Vin = Vout = Vinv
C. Vin < Vout > Vinv
D. Vin > Vout = Vinv
Answer: B
For cascade inverters without degradation of levels, the relation suitable and required is
Vin = Vout = Vinv.
Cascade multilevel inverters have been developed for electric utility applications.
A cascade M-level inverter consists of (M-1)/2 H-bridges in which each bridge’s dc voltage is supported by its own dc capacitor.
