A. rise time
B. fall time
C. all of the mentioned
D. none of the mentioned
Answer: A
Rise time is slower by a factor of 2.5 than fall time.
22. Condition for achieving symmetrical operation is _______
A. Wp = Wn
B. Wp greater than Wn
C. Wp lesser than Wn
D. Wp lesser than 2Wn
Answer: B
The condition for achieving symmetrical operation is Wp = 2.5 Wn.
23. Rise time and fall time is _____ to load capacitance CL.
A. directly proportional
B. inversely proportional
C. exponentially equal
D. not related
Answer: A
Rise time and the fall time are directly proportional to load capacitance CL.
24. Rise time and the fall time is ________ to Vdd.
A. directly proportional
B. inversely proportional
C. exponentially equal
D. not related
Answer: B
Rise time and fall time are inversely proportional to Vdd. This shows that if Vdd is reduced fall time and rise time increase.
25. For shorter delays ______ resistance should be used.
A. smaller
B. larger
C. does not depend on the resistance
D. very large
Answer: A
For shorter delays, low resistance should be used as delay is directly proportional or related to resistance.
26. To reduce the resistance value of inverters, channels must be made __________
A. wider
B. narrower
C. lengthier
D. shorter
Answer: A
Channels must be made wider to reduce the resistance value that is low resistance values for Zp.u. ad Zp.d. implies low L: W ratios and thus consequently an inverter to meet this need occupies a larger area.
27. As width increases, capacitive load __________
A. increases
B. decreases
C. does not change
D. exponentially increases
Answer: A
As the width of the channel increases, capacitive load also increases and with this, the area occupied also increases. The rate at which the width increases affects the stages N and load capacitance.
28. Delay per stage for logic 0 to 1 transition can be given as __________
A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer: A
Delay per stage for logic 0 to 1 transition can be given as fƮ. With large f, N decreases but delay per stage increases.
29. Delay per stage for logic 1 to 0 transition can be given as __________
A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer: D
Delay per stage for logic 1 to 0 transition can be given as 4fƮ. Using the delay for the transition from 1 to 0 and 0 to 1 total nMOS delay can be obtained.
30. What is the total delay of an nMOS pair?
A. fƮ
B. 2fƮ
C. 5fƮ
D. 4fƮ
Answer: C
The total delay of an nMOS pair is equal to 5fƮ. This can be calculated by knowing the delay per stage, that is for two different transitions from 0 to 1 and vice versa.
