VLSI Clocked Sequential Circuit MCQ Quiz – Objective Question with Answer for VLSI Clocked Sequential Circuit

1. Clocked sequential circuits are

A. two-phase overlapping clock
B. two-phase non-overlapping clock
C. four-phase overlapping clock
D. four-phase non-overlapping clock

Answer: B

Clocked sequential circuits are two-phase non-overlapping clock signals. Clock signals are distributed in two wires and it is non-overlapping.

 

2. Which are easier to design?

A. clocked circuits
B. asynchronous sequential circuits
C. clocked circuits with buffer
D. asynchronous sequential circuits with buffers

Answer: A

Clocked circuitry is easier to design than asynchronous sequential circuits. But it is slower than the asynchronous sequential circuit.

 

3. ___________ is used to drive high capacitance load.

A. single polar capability
B. bipolar capability
C. tripolar capability
D. bi and tripolar capability

Answer: B

Bipolar capability is used to drive a high capacitance load. It can handle high loads as it is done by BiCMOS NAND gate logic.

 

4. As the temperature is increased, storage time ________

A. halved
B. doubled
C. does not change
D. tripled

Answer: A

As the temperature is increased, storage time is halved. It is inversely proportional to the storage time.

 

5. Inverting dynamic register element consists of __________ transistors for nMOS and _________ for CMOS.

A. two, three
B. three, two
C. three, four
D. four, three

Answer: C

The dynamic register element consists of three transistors for nMOS and four for CMOS.

 

6. Non inverting dynamic register storage cell consists of _________ transistors for nMOS and _________ for CMOS.

A. six, eight
B. eight, six
C. five, six
D. six, five

Answer: A

Non-inverting dynamic register storage cell consists of six transistors for nMOS and eight for CMOS.

 

7. Register cell consists of

A. inverter
B. pass transistor
C. inverter & pass transistor
D. none of the mentioned

Answer: C

Register cell consists of an inverter and a pass transistor or a transmission gate. The dynamic register cell consists of stick/circuit notation.

 

8. In a four-bit dynamic shift register basic nMOS transistors or inverters are connected in

A. series
B. cascade
C. parallel
D. series and parallel

Answer: B

The basic inverters or nMOS transistors are connected in cascade to obtain four-bit dynamic shift register.

 

9. In four-bit dynamic shift register output is obtained

A. parallel output at inverters 1, 3, 5, 7
B. parallel output at inverters 1, 5, 8
C. parallel output at all inverters
D. parallel output at inverters 2, 4, 6, 8

Answer: D

In the four-bit dynamic shift register, the output is obtained parallelly at inverters 2, 4, 6, 8.

 

10. For signals which are updated frequently _____ is used.

A. static storage
B. dynamic storage
C. static and dynamic storage
D. buffer

Answer: B

For signals which are updated frequently dynamic storage elements are used. It can be done at < 0.25 msec intervals.

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