VLSI Combinational Logic Testing MCQ Quiz – Objective Question with Answer for VLSI Combinational Logic Testing

1. The input signal combination in exhaustive testing is given as

A. 2N
B. 21/N
C. 2(M+N)
D. 1/2N

For testing an N input circuit using exhaustive testing, the total number of input combinations can be given as 2N.

2. Observability is the process of

A. checking all inputs
B. checking all outputs
C. checking all possible inputs
D. checking errors and performance

Observability is the process of observing outputs for all the input combinations.

3. Exhaustive testing is suitable when N is

A. small
B. large
C. any value for N
D. very large

Exhaustive testing is the process where all possible input combinations are used. This is suitable when N is relatively small.

4. Test vectors in sensitized path-based testing is generated

A. before enumerating faults
B. after enumerating faults
C. after designing
D. before designing

In sensitized path-based testing, test vectors are generated after enumerating the possible faults because many patterns may not occur during the application of the circuit.

5. To propagate the fault along the selected path to primary output, setting _____ is done.

A. AND to 1
B. OR to 1
C. NOR to 1
D. NAND to 0

Inputs of another gate are determined so as to propagate the fault signal along the selected path to the primary output of the circuit. This is done by setting AND/NAND to 1 and OR/NOR to 0.

6. In consistency/ justification, tracking is done
A. forward from gate input to primary input
B. backward from the gate input to the primary output
C. backward from the gate input to primary input
D. forward from gate output to the primary output

The consistency step finds the input patterns to realize all the necessary values. This is done by tracking backward from gate input to the primary input of the logic.

7. In D-algorithm, a particular ______ fault is detected by examining the _____ conditions.

A. internal, output
B. internal, input
C. external, output
D. external, input

In a circuit comprising combinational logic, D-algorithm aims at detecting a particular internal fault by examining the output conditions.

8. D-algorithm is based on

A. existence of one fault machine
B. existence of one good machine
C. existence of one fault and one good machine
D. existence of two fault machines alone

D-algorithm is based on the hypothesis of the existence of two machines – one good machine and one faulty machine.

9. The existence of a fault in the faulty machine causes a discrepancy in the behavior of the circuit for all values on inputs.

A. true
B. false

The existence of a fault in a faulty machine causes a discrepancy in its behavior and that of the good machine for some particular values of inputs.

10. In D-algorithm, the discrepancy is driven to _____ and observed and thus detected.

A. all inputs
B. particular inputs
C. output
D. end of the circuit